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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114734] [11 regression] RISC-V rv64gcv_zvl256b
 miscompile with -flto -O3 -mrvv-vector-bits=zvl since r8-6047-g65dd1346027bb5
Date: Fri, 21 Jun 2024 09:36:19 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114734

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|ASSIGNED                    |RESOLVED

--- Comment #23 from Richard Biener <rguenth at gcc dot gnu.org> ---
Fixed.=