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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114801] [14/15 Regression] arm: ICE in
 find_cached_value, at rtx-vector-builder.cc:100 with MVE intrinsics
Date: Mon, 29 Apr 2024 16:07:07 +0000
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X-Bugzilla-Version: 14.0
X-Bugzilla-Keywords: ice-on-valid-code
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114801

--- Comment #29 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
With
--- a/gcc/config/arm/arm-mve-builtins.cc
+++ b/gcc/config/arm/arm-mve-builtins.cc
@@ -2100,7 +2100,22 @@ function_expander::add_input_operand (insn_code icod=
e,
rtx x)
       mode =3D GET_MODE (x);
     }
   else if (VALID_MVE_PRED_MODE (mode))
-    x =3D gen_lowpart (mode, x);
+    {
+      if (CONST_INT_P (x) && (mode =3D=3D V8BImode || mode =3D=3D V4BImode=
))
+       {
+         /* In V8BI or V4BI each element has 2 or 4 bits, if those
+            bits aren't all the same, gen_lowpart might ICE.  */
+         unsigned HOST_WIDE_INT xi =3D UINTVAL (x);
+         if ((xi & 0x5555) !=3D ((xi >> 1) & 0x5555)
+             || (mode =3D=3D V4BImode
+                 && (xi & 0x3333) !=3D ((xi >> 2) & 0x3333)))
+           x =3D force_reg (HImode, x);
+       }
+      else if (SUBREG_P (x))
+       /* gen_lowpart on a SUBREG can ICE.  */
+       x =3D force_reg (GET_MODE (x), x);
+      x =3D gen_lowpart (mode, x);
+    }

   m_ops.safe_grow (m_ops.length () + 1, true);
   create_input_operand (&m_ops.last (), x, mode);=