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From: "clyon at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114801] [14/15 Regression] arm: ICE in
 find_cached_value, at rtx-vector-builder.cc:100 with MVE intrinsics
Date: Mon, 29 Apr 2024 13:41:55 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114801

--- Comment #19 from Christophe Lyon <clyon at gcc dot gnu.org> ---
So basically values such as 0xcccc are not UB and we want to accept them.

I tested:
diff --git a/gcc/rtx-vector-builder.cc b/gcc/rtx-vector-builder.cc
index 9509d9fc453..f89aa717903 100644
--- a/gcc/rtx-vector-builder.cc
+++ b/gcc/rtx-vector-builder.cc
@@ -96,8 +96,6 @@ rtx_vector_builder::find_cached_value ()
=C2=A0 =C2=A0 =C2=A0 =C2=A0 return CONSTM1_RTX (m_mode);
=C2=A0 =C2=A0 =C2=A0 =C2=A0else if (elt =3D=3D const0_rtx)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 return CONST0_RTX (m_mode);
- =C2=A0 =C2=A0 =C2=A0else
- =C2=A0 =C2=A0 =C2=A0 gcc_unreachable ();
=C2=A0 =C2=A0 =C2=A0}

   /* We can be called before the global vector constants are set up,
diff --git a/gcc/config/arm/arm-mve-builtins.cc
b/gcc/config/arm/arm-mve-builtins.cc
index 6a5775c67e5..6dc0b603dad 100644
--- a/gcc/config/arm/arm-mve-builtins.cc
+++ b/gcc/config/arm/arm-mve-builtins.cc
@@ -2205,7 +2205,13 @@ function_expander::add_input_operand (insn_code icod=
e,
rtx x)
=C2=A0 =C2=A0 =C2=A0 =C2=A0mode =3D GET_MODE (x);
=C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0else if (VALID_MVE_PRED_MODE (mode))
- =C2=A0 =C2=A0x =3D gen_lowpart (mode, x);
+ =C2=A0 =C2=A0{
+ =C2=A0 =C2=A0 =C2=A0if (SUBREG_P (x))
+ =C2=A0 =C2=A0 =C2=A0 /* gen_lowpart on a SUBREG can ICE. =C2=A0*/
+ =C2=A0 =C2=A0 =C2=A0 x =3D force_reg (GET_MODE (x), x);
+
+ =C2=A0 =C2=A0 =C2=A0x =3D gen_lowpart (mode, x);
+ =C2=A0 =C2=A0}

=C2=A0 =C2=A0m_ops.safe_grow (m_ops.length () + 1, true);
   create_input_operand (&m_ops.last (), x, mode);


And it works: we generate
mov     r2, #52428 for 0xcccc
mov     r3, #43690 for 0xaaaa

But I guess removing the call to gcc_unreachable breaks a strong assumption=
 in
many places?=