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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/114810] [14 Regression] internal compiler
 error: in lra_split_hard_reg_for, at lra-assigns.cc:1868  (unable to find a
 register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2
 -mbmi -fno-exceptions -fno-plt
Date: Mon, 22 Apr 2024 21:36:01 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114810

--- Comment #8 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to Uro=C5=A1 Bizjak from comment #7)
> (define_insn_and_split "*andn<dwi>3_doubleword_bmi"
>   [(set (match_operand:<DWI> 0 "register_operand" "=3D&r,r,r")
> 	(and:<DWI>
> 	  (not:<DWI> (match_operand:<DWI> 1 "register_operand" "r,0,r"))
> 	  (match_operand:<DWI> 2 "nonimmediate_operand" "ro,ro,0")))
>    (clobber (reg:CC FLAGS_REG))]
>=20
> where the problematic alternative (=3D&r,r,ro) allows a memory input in i=
ts
> operand 2 constraint. The allocator could spill a DImode value to a stack=
 in
> advance and reload the value from the memory in this particular alternati=
ve.

So, given the known ia32 register starvation, can't we split that first
alternative to
=3D&r,r,o with "nox64" isa and =3D&r,r,ro with "x64" isa?=