From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 7C4BD3858D38; Tue, 23 Apr 2024 06:02:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7C4BD3858D38 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1713852156; bh=pY8P7LdNcvUzLmZDw+gu0HQQ4wiO+11fAqd/0Vq4mgo=; h=From:To:Subject:Date:In-Reply-To:References:From; b=aJ4cBio9yNueuoMTI7LNy99pJ0PWS1TrZQzu4yC7vKnS7r8MNsBzMonIMRXac0/Kj R9cxwD9Vy7NOncZeAJ6VPmmO819Li33n9AXuN6RQ5zbjOEhdYfTlVklk/AQCqmEzBN 6tmQ0rkwridMC2lyyRKaYKY7kdoZTKol51wnHPiE= From: "ubizjak at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/114810] [14 Regression] internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868 (unable to find a register to spill) {*andndi3_doubleword_bmi} with -m32 -mstackrealign -O2 -mbmi -fno-exceptions -fno-plt Date: Tue, 23 Apr 2024 06:02:36 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 14.0 X-Bugzilla-Keywords: ra X-Bugzilla-Severity: normal X-Bugzilla-Who: ubizjak at gmail dot com X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P1 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 14.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114810 --- Comment #12 from Uro=C5=A1 Bizjak --- (In reply to Vladimir Makarov from comment #9) > (In reply to Uro=C5=A1 Bizjak from comment #7) > > > >=20 > > Please note that the insn is defined as: > >=20 > > (define_insn_and_split "*andn3_doubleword_bmi" > > [(set (match_operand: 0 "register_operand" "=3D&r,r,r") > > (and: > > (not: (match_operand: 1 "register_operand" "r,0,r")) > > (match_operand: 2 "nonimmediate_operand" "ro,ro,0"))) > > (clobber (reg:CC FLAGS_REG))] > >=20 > > where the problematic alternative (=3D&r,r,ro) allows a memory input in= its > > operand 2 constraint. The allocator could spill a DImode value to a sta= ck in > > advance and reload the value from the memory in this particular alterna= tive. >=20 > That is not how LRA (and the old reload) works. If an operand matches the > constraint (r in ro), it does not change its location (do reloads). >=20 > In general, it is possible to implement reloads for operands already matc= hed > to a constraint but this would significantly complicate already too > complicated code. And probably heuristics based on reload costs would > reject such reloads anyway. >=20 > I probably could implement reg starvation recognition in process_alt_oper= and > and penalize the alternative and most probably it will not affect other > targets. Still it is not easy because of different possible class subsets > or intersections. >=20 > Still I think Jakub's solution is reasonable at this stage. If I impleme= nt > my proposed solution we could commit it after the release. Yes, I agree. Not knowing the internals of the RA, it looked "obvious" that= RA could use memory operand here, and using this solution in the target-independent code could solve the issue also for other register starv= ed targets. Another long-term improvement in the RA could be allocating multi-regs in a random order. As far as x86 is concerned, apart from passing function parameters in registers and perhaps some asm constraint ("A"), there is no = need for double-word registers to be allocated in any specific order. The double-word value could be allocated in {hi,lo} register tuplet, where hi a= nd lo can be any register. Using this approach, the RA could allocate a double-word value also in [01]2[34]5 situation.=