From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 27F50385E83E; Thu, 2 May 2024 19:07:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 27F50385E83E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1714676833; bh=/d24RitBB4Y9UDhr/t+Gs3l+41IkL4GH2XzMPnGtNYg=; h=From:To:Subject:Date:In-Reply-To:References:From; b=mKl1NofYtC5ale2qsl+To0TQoU1AuPvMYbSgFUn/vFxOTQg5MfvEYNPE1KhZ+4VRE VpLRusKCO0HXmy7h1i5rgBxA3UFRRB/D30CezWV6zABs0YwZED5Ct3zqfy4uK4lMv5 TnFT8tTcEyAMtFfblihStDOZpEEhTWp4OF+zg0Nk= From: "pinskia at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug middle-end/114923] gcc ignores escaping pointer and applies invalid optimization Date: Thu, 02 May 2024 19:07:10 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: middle-end X-Bugzilla-Version: unknown X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: pinskia at gcc dot gnu.org X-Bugzilla-Status: RESOLVED X-Bugzilla-Resolution: INVALID X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_status resolution Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114923 Andrew Pinski changed: What |Removed |Added ---------------------------------------------------------------------------- Status|UNCONFIRMED |RESOLVED Resolution|--- |INVALID --- Comment #5 from Andrew Pinski --- Escape means something different from memory being written. In C (and C++), memory writes to some variable is modeled such that it is n= ot known to write to another location So you need to add a compiler barrier here. Note `atomic_signal_fence (memory_order_relaxed)` might be enough. Note also the order of the writes to reg1 and reg2 might happen in a different order = in HW so you need to have a full (HW) write barrier between them to make sure = the write is done in the correct order.=