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From: "nfxjfg at googlemail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/114923] gcc ignores escaping pointer and applies invalid optimization
Date: Fri, 03 May 2024 00:30:15 +0000	[thread overview]
Message-ID: <bug-114923-4-OsxsNrIKwO@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-114923-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114923

--- Comment #9 from nfxjfg at googlemail dot com ---
Oh, I completely missed that your statement was restricted to "in HW". Normally
there are mechanisms in place that make all CPU-level memory accesses to
registers strictly ordered. (In our hardware that is also the case.) I panicked
because you seemed to imply that even the compiler can reorder accesses to reg1
and reg2, but this isn't the case according to you, the gcc docs, and maybe the
standard. Sorry about that.

I suppose it's regrettable that C and gcc do not consider the possibility that
passing an address to a register (which volatile is pretty much the only useful
thing for) does not imply that the memory at that address may change. But that
seems to be the conclusion here.

      parent reply	other threads:[~2024-05-03  0:30 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-02 12:51 [Bug c/114923] New: " nfxjfg at googlemail dot com
2024-05-02 12:52 ` [Bug c/114923] " nfxjfg at googlemail dot com
2024-05-02 13:24 ` amonakov at gcc dot gnu.org
2024-05-02 13:44 ` nfxjfg at googlemail dot com
2024-05-02 13:56 ` amonakov at gcc dot gnu.org
2024-05-02 19:07 ` [Bug middle-end/114923] " pinskia at gcc dot gnu.org
2024-05-02 19:15 ` pinskia at gcc dot gnu.org
2024-05-02 23:03 ` nfxjfg at googlemail dot com
2024-05-02 23:42 ` pinskia at gcc dot gnu.org
2024-05-03  0:30 ` nfxjfg at googlemail dot com [this message]

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