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From: "tnfchris at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug tree-optimization/114932] Improvement in CHREC can give large
 performance gains
Date: Fri, 03 May 2024 08:09:53 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114932

--- Comment #3 from Tamar Christina <tnfchris at gcc dot gnu.org> ---
(In reply to Andrew Pinski from comment #2)
> > which is harder for prefetchers to follow.
>=20
> This seems like a limitation in the HW prefetcher rather than anything el=
se.
> Maybe the cost model for addressing mode should punish base+index if so.
> Many HW prefetchers I know of are based on the final VA (or even PA) rath=
er
> looking at the instruction to see if it increments or not ...

That was the first thing we tried, and even increasing the cost of
register_offset to something ridiculously high doesn't change a thing.

IVopts thinks it needs to use it and generates:

  _1150 =3D (voidD.26 *) _1148;
  _1152 =3D (sizetype) l0_78(D);
  _1154 =3D _1152 * 324;
  _1156 =3D _1154 + 216;
  # VUSE <.MEM_421>
  vect__349.614_1418 =3D MEM <vector(2) integer(kind=3D4)D.9> [(integer(kin=
d=3D4)D.9
*)_1150 + _1156 * 1 clique 2 base 0];

Hence the bug report to see what's going on.=