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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114942] [14/15 Regression] ICE on valid code at -O1 with "-fno-tree-sra -fno-guess-branch-probability": in extract_constrain_insn, at recog.cc:2713
Date: Sat, 04 May 2024 08:28:49 +0000	[thread overview]
Message-ID: <bug-114942-4-0gCht7jIIH@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-114942-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114942

--- Comment #2 from Uroš Bizjak <ubizjak at gmail dot com> ---
This is the insn in question:

;; Alternative 1 is needed to work around LRA limitation, see PR82524.
 (define_insn_and_split "*<code>qi_ext<mode>_1_slp"
   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+Q,&Q"))
         (any_logic:QI
           (subreg:QI
             (match_operator:SWI248 3 "extract_operator"
               [(match_operand 2 "int248_register_operand" "Q,Q")
                (const_int 8)
                (const_int 8)]) 0)
           (match_operand:QI 1 "nonimmediate_operand" "0,!qm")))
    (clobber (reg:CC FLAGS_REG))]

When targeting alternative 1, reload should use some other register for operand
2.

  parent reply	other threads:[~2024-05-04  8:28 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-03 22:13 [Bug rtl-optimization/114942] New: " zhendong.su at inf dot ethz.ch
2024-05-03 22:25 ` [Bug target/114942] [14/15 Regression] " pinskia at gcc dot gnu.org
2024-05-04  8:28 ` ubizjak at gmail dot com [this message]
2024-05-05 19:32 ` ubizjak at gmail dot com
2024-05-07  7:46 ` rguenth at gcc dot gnu.org
2024-05-08 17:11 ` vmakarov at gcc dot gnu.org
2024-05-10 16:29 ` cvs-commit at gcc dot gnu.org
2024-06-17 15:18 ` pinskia at gcc dot gnu.org

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