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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/114988] RISC-V: ICE in intrinsic
 __riscv_vfwsub_wf_f32mf2
Date: Mon, 13 May 2024 14:59:09 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D114988

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:41b3cf262e61aee9d26380f1c820e0eaae740f50

commit r15-435-g41b3cf262e61aee9d26380f1c820e0eaae740f50
Author: Pan Li <pan2.li@intel.com>
Date:   Sat May 11 15:25:28 2024 +0800

    RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar

    For the vfw vx format RVV intrinsic, the scalar type _Float16 also
    requires the zvfh extension.  Unfortunately,  we only check the
    vector tree type and miss the scalar _Float16 type checking.  For
    example:

    vfloat32mf2_t test_vfwsub_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1, si=
ze_t
vl)
    {
      return __riscv_vfwsub_wf_f32mf2(vs2, rs1, vl);
    }

    It should report some error message like zvfh extension is required
    instead of ICE for unreg insn.

    This patch would like to make up such kind of validation for _Float16
    in the RVV intrinsic API.  It will report some error like below when
    there is no zvfh enabled.

    error: built-in function '__riscv_vfwsub_wf_f32mf2(vs2,  rs1,  vl)'
      requires the zvfhmin or zvfh ISA extension

    Passed the rv64gcv fully regression tests, included c/c++/fortran.

            PR target/114988

    gcc/ChangeLog:

            * config/riscv/riscv-vector-builtins.cc
            (validate_instance_type_required_extensions): New func impl to
            validate the intrinisc func type ops.
            (expand_builtin): Validate instance type before expand.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr114988-1.c: New test.
            * gcc.target/riscv/rvv/base/pr114988-2.c: New test.

    Signed-off-by: Pan Li <pan2.li@intel.com>=