[Bug c/115068] New: RISC-V: Illegal instruction of vfwadd

[Bug c/115068] New: RISC-V: Illegal instruction of vfwadd

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115068

            Bug ID: 115068
           Summary: RISC-V: Illegal instruction of vfwadd
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: juzhe.zhong at rivai dot ai
  Target Milestone: ---

#include <stdint.h>
#include <riscv_vector.h>

vfloat64m8_t test_vfwadd_wf_f64m8_m(vbool8_t vm, vfloat64m8_t vs2, float rs1,
size_t vl) {
  return __riscv_vfwadd_wf_f64m8_m(vm, vs2, rs1, vl);
}

char global_memory[1024];
void *fake_memory = (void *)global_memory;

int main ()
{
  asm volatile("fence":::"memory");
  vfloat64m8_t vfwadd_wf_f64m8_m_vd =
test_vfwadd_wf_f64m8_m(__riscv_vreinterpret_v_i8m1_b8(__riscv_vundefined_i8m1()),
__riscv_vundefined_f64m8(), 1.0, __riscv_vsetvlmax_e64m8());
  asm volatile(""::"vr"(vfwadd_wf_f64m8_m_vd):"memory");

  return 0;
}

https://compiler-explorer.com/z/rq7K33zE5

main:
        fence
        lui     a5,%hi(.LC0)
        flw     fa5,%lo(.LC0)(a5)
        vsetvli a5,zero,e32,m4,ta,ma
        vfwadd.wf       v0,v8,fa5,v0.t ---> vd should not be v0.
        li      a0,0
        ret

[Bug target/115068] RISC-V: Illegal instruction of vfwadd

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115068

--- Comment #1 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>:

https://gcc.gnu.org/g:a2fd0812a54cf51520f15e900df4cfb5874b75ed

commit r15-951-ga2fd0812a54cf51520f15e900df4cfb5874b75ed
Author: Robin Dapp <rdapp@ventanamicro.com>
Date:   Mon May 13 13:49:57 2024 +0200

    RISC-V: Do not allow v0 as dest when merging [PR115068].

    This patch splits the vfw...wf pattern so we do not emit e.g. vfwadd.wf
    v0,v8,fa5,v0.t anymore.

    gcc/ChangeLog:

            PR target/115068

            * config/riscv/vector.md:  Split vfw<insn>.wf pattern.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr115068-run.c: New test.
            * gcc.target/riscv/rvv/base/pr115068.c: New test.