[Bug rtl-optimization/115169] New: [14 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[Bug rtl-optimization/115169] New: [14 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[matoro_gcc_bugzilla at matoro dot tk]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

            Bug ID: 115169
           Summary: [14 regression] ICE in loongarch bootstrap with
                    checking: RTL check: expected code 'reg', have
                    'const_int' in rhs_regno, at rtl.h:1934
           Product: gcc
           Version: 14.1.1
            Status: UNCONFIRMED
          Keywords: ice-checking
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: matoro_gcc_bugzilla at matoro dot tk
  Target Milestone: ---
              Host: loongarch64-unknown-linux-gnu
            Target: loongarch64-unknown-linux-gnu
             Build: loongarch64-unknown-linux-gnu

There seems to be a couple RISC-V items with similar stack traces but unsure if
they are the same bug.  Trying to upgrade 13 -> 14 on a 3A5000 and I get a
SIGILL from genmodes, so fell back to checking build and unfortunately
encountered an ICE there as well.  Unsure if this is the cause of the SIGILL or
not, so one bug at a time.

/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/build/./gcc/xgcc
-B/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/build/./gcc/
-B/usr/loongarch64-unknown-linux-gnu/bin/
-B/usr/loongarch64-unknown-linux-gnu/lib/ -isystem
/usr/loongarch64-unknown-linux-gnu/include -isystem
/usr/loongarch64-unknown-linux-gnu/sys-include -fmultiflags   -fno-checking -g
-ggdb3 -O2 -O2  -g -ggdb3 -O2 -DIN_GCC   -W -Wall -Wno-narrowing
-Wwrite-strings -Wcast-qual -Wno-format -Wstrict-prototypes
-Wmissing-prototypes -Wold-style-definition  -isystem ./include  -fpic -g
-DIN_LIBGCC2 -fbuilding-libgcc -fno-stack-protector -fno-stack-clash-protection
 -fpic -I. -I. -I../.././gcc
-I/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/libgcc
-I/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/libgcc/.
-I/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/libgcc/../gcc
-I/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/libgcc/../include
 -DHAVE_CC_TLS   -o _mulvdi3.o -MT _mulvdi3.o -MD -MP -MF _mulvdi3.dep
-DL_mulvdi3 -c
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/libgcc/libgcc2.c
-fvisibility=hidden -DHIDE_EXPORTS
during RTL pass: ce1
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/libgcc/libgcc2.c:
In function ‘__mulvti3’:
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/libgcc/libgcc2.c:376:1:
internal compiler error: RTL check: expected code 'reg', have 'const_int' in
rhs_regno, at rtl.h:1934
  376 | }
      | ^
0x55555776ca7b rtl_check_failed_code1(rtx_def const*, rtx_code, char const*,
int, char const*)
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/rtl.cc:770
0x55555777e457 rhs_regno(rtx_def const*)
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/rtl.h:1934
0x5555584be663 rhs_regno(rtx_def const*)
        ./genrtl.h:38
0x5555584be663 loongarch_expand_conditional_move(rtx_def**)
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/config/loongarch/loongarch.cc:5355
0x5555589f5293 gen_movdicc(rtx_def*, rtx_def*, rtx_def*, rtx_def*)
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/config/loongarch/loongarch.md:2556
0x555557e74ceb maybe_expand_insn(insn_code, unsigned int, expand_operand*)
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/optabs.cc:8275
0x555557e74ceb emit_conditional_move_1
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/optabs.cc:5249
0x555557e751c7 emit_conditional_move(rtx_def*, rtx_comparison, rtx_def*,
rtx_def*, machine_mode, int)
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/optabs.cc:5162
0x555558c3c02b noce_emit_cmove
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/ifcvt.cc:1777
0x555558c4062b noce_try_cmove_arith
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/ifcvt.cc:2363
0x555558c4644f noce_process_if_block
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/ifcvt.cc:4161
0x555558c4644f noce_find_if_block
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/ifcvt.cc:4716
0x555558c479c3 find_if_header
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/ifcvt.cc:4921
0x555558c479c3 if_convert
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/ifcvt.cc:6068
0x555558c48b97 rest_of_handle_if_conversion
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/ifcvt.cc:6133
0x555558c48b97 execute
       
/var/tmp/portage/sys-devel/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/ifcvt.cc:6172

[Bug rtl-optimization/115169] [14 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[matoro_gcc_bugzilla at matoro dot tk]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

matoro <matoro_gcc_bugzilla at matoro dot tk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |matoro_gcc_bugzilla@matoro.
                   |                            |tk

--- Comment #1 from matoro <matoro_gcc_bugzilla at matoro dot tk> ---
Created attachment 58256
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58256&action=edit
build.log and emerge --info

[Bug target/115169] [14 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[matoro_gcc_bugzilla at matoro dot tk]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

--- Comment #2 from matoro <matoro_gcc_bugzilla at matoro dot tk> ---
Created attachment 58257
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58257&action=edit
preprocessed source

[Bug target/115169] [14 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[matoro_gcc_bugzilla at matoro dot tk]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

--- Comment #3 from matoro <matoro_gcc_bugzilla at matoro dot tk> ---
Minimal command to trigger: ./gcc/xgcc -O1 -c _mulvdi3.i -B./gcc/

[Bug target/115169] [14 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[matoro_gcc_bugzilla at matoro dot tk]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

--- Comment #4 from matoro <matoro_gcc_bugzilla at matoro dot tk> ---
Minimized:

int __mulvti3_uu_0, __mulvti3_vv_0_1, __mulvti3_w0_1;
int __mulvti3() {
  if (__builtin_expect(__mulvti3_uu_0, 1)) {
    int w1_0_1;
    if (__mulvti3_vv_0_1)
      w1_0_1 -= __mulvti3_uu_0;
    if (__builtin_expect(w1_0_1, 1))
      return __mulvti3_w0_1;
  }
}

[Bug target/115169] [14/15 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
   Target Milestone|---                         |14.2
             Status|UNCONFIRMED                 |NEW
            Summary|[14 regression] ICE in      |[14/15 regression] ICE in
                   |loongarch bootstrap with    |loongarch bootstrap with
                   |checking: RTL check:        |checking: RTL check:
                   |expected code 'reg', have   |expected code 'reg', have
                   |'const_int' in rhs_regno,   |'const_int' in rhs_regno,
                   |at rtl.h:1934               |at rtl.h:1934
   Last reconfirmed|                            |2024-05-21

--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed via visual inspecting the code:
```
(define_expand "mov<mode>cc"
  [(set (match_operand:GPR 0 "register_operand")
        (if_then_else:GPR (match_operator 1 "comparison_operator"
                         [(match_operand:GPR 2 "reg_or_0_operand")
                          (match_operand:GPR 3 "reg_or_0_operand")])))]

```
```
  rtx op0 = XEXP (operands[1], 0);
  rtx op1 = XEXP (operands[1], 1);
...

      if ((REGNO (op0) == REGNO (operands[2])
           || (REGNO (op1) == REGNO (operands[3]) && (op1 != const0_rtx)))
          && (GET_MODE_SIZE (GET_MODE (op0)) < word_mode))
        {


```

There is no check to make sure op0/op1/operands[2]/operands[3] are registers
before calling REGNO on them.

This code was introduced by r14-3511-gc28c579f0dd9cd .

[Bug target/115169] [14/15 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[xry111 at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

Xi Ruoyao <xry111 at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |xry111 at gcc dot gnu.org

--- Comment #6 from Xi Ruoyao <xry111 at gcc dot gnu.org> ---
I'll take a look.

[Bug target/115169] [14/15 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[xry111 at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

Xi Ruoyao <xry111 at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED

[Bug target/115169] [14/15 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

--- Comment #7 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Xi Ruoyao <xry111@gcc.gnu.org>:

https://gcc.gnu.org/g:ded91d857772c0183cc342cdc54d9128f6c57fa2

commit r15-856-gded91d857772c0183cc342cdc54d9128f6c57fa2
Author: Xi Ruoyao <xry111@xry111.site>
Date:   Wed May 22 09:29:43 2024 +0800

    LoongArch: Guard REGNO with REG_P in loongarch_expand_conditional_move
[PR115169]

    gcc/ChangeLog:

            PR target/115169
            * config/loongarch/loongarch.cc
            (loongarch_expand_conditional_move): Guard REGNO with REG_P.

[Bug target/115169] [14/15 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

--- Comment #8 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-14 branch has been updated by Xi Ruoyao <xry111@gcc.gnu.org>:

https://gcc.gnu.org/g:e78980fdd5e82e09e26f524e98ad9cd90a29c1c4

commit r14-10249-ge78980fdd5e82e09e26f524e98ad9cd90a29c1c4
Author: Xi Ruoyao <xry111@xry111.site>
Date:   Wed May 22 09:29:43 2024 +0800

    LoongArch: Guard REGNO with REG_P in loongarch_expand_conditional_move
[PR115169]

    gcc/ChangeLog:

            PR target/115169
            * config/loongarch/loongarch.cc
            (loongarch_expand_conditional_move): Guard REGNO with REG_P.

    (cherry picked from commit ded91d857772c0183cc342cdc54d9128f6c57fa2)

[Bug target/115169] [14/15 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[xry111 at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

Xi Ruoyao <xry111 at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #9 from Xi Ruoyao <xry111 at gcc dot gnu.org> ---
Fixed.

For the SIGILL issue note that in GCC 14 the default of -march is raised from
loongarch64 to la64v1.0 which implies LSX.  So I'd suggest to check if
CPU_HAS_LSX is enabled in the kernel configuration first.

[Bug target/115169] [14/15 regression] ICE in loongarch bootstrap with checking: RTL check: expected code 'reg', have 'const_int' in rhs_regno, at rtl.h:1934

[matoro_gcc_bugzilla at matoro dot tk]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115169

--- Comment #10 from matoro <matoro_gcc_bugzilla at matoro dot tk> ---
(In reply to Xi Ruoyao from comment #9)
> Fixed.
> 
> For the SIGILL issue note that in GCC 14 the default of -march is raised
> from loongarch64 to la64v1.0 which implies LSX.  So I'd suggest to check if
> CPU_HAS_LSX is enabled in the kernel configuration first.

Thank you, that indeed was it!  I'll make sure we get this kernel check sorted
out downstream.