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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug rtl-optimization/115297] [14/15 regression] alpha: ICE in
 simplify_subreg, at simplify-rtx.cc:7554 with -O1
Date: Mon, 03 Jun 2024 14:13:18 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D115297

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-12 branch has been updated by Uros Bizjak <uros@gcc.gnu.or=
g>:

https://gcc.gnu.org/g:c6c2a6cebabc5f78cef3d81cedb4b3b578478b9f

commit r12-10486-gc6c2a6cebabc5f78cef3d81cedb4b3b578478b9f
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri May 31 15:52:03 2024 +0200

    alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]

    any_divmod instructions are modelled with invalid RTX:

      [(set (match_operand:DI 0 "register_operand" "=3Dc")
            (sign_extend:DI (match_operator:SI 3 "divmod_operator"
                            [(match_operand:DI 1 "register_operand" "a")
                             (match_operand:DI 2 "register_operand" "b")])))
       (clobber (reg:DI 23))
       (clobber (reg:DI 28))]

    where SImode divmod_operator (div,mod,udiv,umod) has DImode operands.

    Wrap input operand with truncate:SI to make machine modes consistent.

            PR target/115297

    gcc/ChangeLog:

            * config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode
            operands 3 and 4 with truncate:SI RTX.
            (*divmodsi_internal_er): Ditto for operands 1 and 2.
            (*divmodsi_internal_er_1): Ditto.
            (*divmodsi_internal): Ditto.
            * config/alpha/constraints.md ("b"): Correct register
            number in the description.

    gcc/testsuite/ChangeLog:

            * gcc.target/alpha/pr115297.c: New test.

    (cherry picked from commit 0ac802064c2a018cf166c37841697e867de65a95)=