[Bug rtl-optimization/115297] New: [14 regression] alpha: ICE in simplify_subreg, at simplify-rtx.cc:7554 with -O1

[Bug rtl-optimization/115297] New: [14 regression] alpha: ICE in simplify_subreg, at simplify-rtx.cc:7554 with -O1

[matoro_gcc_bugzilla at matoro dot tk]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115297

            Bug ID: 115297
           Summary: [14 regression] alpha: ICE in simplify_subreg, at
                    simplify-rtx.cc:7554 with -O1
           Product: gcc
           Version: 14.1.1
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: matoro_gcc_bugzilla at matoro dot tk
  Target Milestone: ---
            Target: alpha-unknown-linux-gnu

Created attachment 58314
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58314&action=edit
gdb context and complete backtrace

Found this while building kernel with gcc-14.  This reproduces on cross, so
using that as an example.

Minimized:

enum { BPF_F_USER_BUILD_ID } __bpf_get_stack_size;
long __bpf_get_stack_flags, bpf_get_stack___trans_tmp_2;
void bpf_get_stack() {
  unsigned elem_size;
  int err = elem_size = __bpf_get_stack_flags ?: sizeof(long);
  if (__builtin_expect(__bpf_get_stack_size % elem_size, 0))
    bpf_get_stack___trans_tmp_2 = err;
}

$ alpha-unknown-linux-gnu-gcc-14 -O1 -c stackmap.i
during RTL pass: combine
stackmap.i: In function ‘bpf_get_stack’:
stackmap.i:8:1: internal compiler error: in simplify_subreg, at
simplify-rtx.cc:7554
    8 | }
      | ^

Backtrace summary (more detailed bt with locals and snippets in attachment):

#0  internal_error (gmsgid=0x1033e41b0 "in %s, at %s:%d") at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/diagnostic.cc:2227
#1  0x0000000102ff9cac in fancy_abort (file=0x103272d20
"/var/tmp/portage/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/work/gcc-14-20240518/gcc/simplify-rtx.cc",
line=7554, 
    function=0x1032731f0 "simplify_subreg") at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/diagnostic.cc:2353
#2  0x00000001017b5ea4 in simplify_context::simplify_subreg
(this=0x7fffffff9f00, outermode=E_DImode, op=0x7ffff5448c28,
innermode=E_SImode, byte=...)
    at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/simplify-rtx.cc:7554
#3  0x00000001017b8da8 in simplify_context::simplify_subreg
(this=0x7fffffff9f00, outermode=E_DImode, op=0x7ffff5449ff0,
innermode=E_SImode, byte=...)
    at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/simplify-rtx.cc:7804
#4  0x00000001017b988c in simplify_context::simplify_gen_subreg
(this=0x7fffffff9f00, outermode=E_DImode, op=0x7ffff5449ff0,
innermode=E_SImode, byte=...)
    at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/simplify-rtx.cc:7875
#5  0x0000000100bb6224 in simplify_gen_subreg (outermode=E_DImode,
op=0x7ffff5449ff0, innermode=E_SImode, byte=...)
    at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/rtl.h:3552
#6  0x00000001028f87dc in if_then_else_cond (x=0x7ffff5449f60,
ptrue=0x7fffffffa528, pfalse=0x7fffffffa538)
    at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/combine.cc:9423
#7  0x00000001028f55ec in if_then_else_cond (x=0x7ffff5449f78,
ptrue=0x7fffffffa948, pfalse=0x7fffffffa958)
    at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/combine.cc:9286
#8  0x00000001028f55ec in if_then_else_cond (x=0x7ffff5449f90,
ptrue=0x7fffffffb148, pfalse=0x7fffffffb150)
    at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/combine.cc:9286
#9  0x00000001028bf07c in combine_simplify_rtx (x=0x7ffff5449f90,
op0_mode=E_VOIDmode, in_dest=false, in_cond=false)
    at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/combine.cc:5758
#10 0x00000001028bc3d8 in subst (x=0x7ffff5449f90, from=0x7ffff54488c8,
to=0x7ffff5451920, in_dest=false, in_cond=false, unique_copy=false)
    at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/combine.cc:5619
#11 0x00000001028bba88 in subst (x=0x7ffff5448cb8, from=0x7ffff54488c8,
to=0x7ffff5451920, in_dest=false, in_cond=false, unique_copy=false)
    at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/combine.cc:5546
#12 0x00000001028babe8 in subst (x=0x7ffff54a68a0, from=0x7ffff54488c8,
to=0x7ffff5451920, in_dest=false, in_cond=false, unique_copy=false)
    at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/combine.cc:5480
#13 0x000000010289ba0c in try_combine (i3=0x7ffff54e0540, i2=0x7ffff54e0500,
i1=0x7ffff54e06c0, i0=0x0, new_direct_jump_p=0x7fffffffe2df,
last_combined_insn=0x7ffff54e0540)
    at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/combine.cc:3349
#14 0x000000010288c22c in combine_instructions (f=0x7ffff54009a0, nregs=88) at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/combine.cc:1285
#15 0x0000000102933030 in rest_of_handle_combine () at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/combine.cc:15114
#16 0x00000001029331d0 in (anonymous namespace)::pass_combine::execute
(this=0x103922900) at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/combine.cc:15158
#17 0x000000010150c264 in execute_one_pass (pass=0x103922900) at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/passes.cc:2647
#18 0x000000010150c7c4 in execute_pass_list_1 (pass=0x103922900) at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/passes.cc:2756
#19 0x000000010150c80c in execute_pass_list_1 (pass=0x103921d60) at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/passes.cc:2757
#20 0x000000010150c8ac in execute_pass_list (fn=0x7ffff5670000,
pass=0x10391d3f0) at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/passes.cc:2767
#21 0x0000000100cb35dc in cgraph_node::expand (this=0x7ffff56a0000) at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/cgraphunit.cc:1845
#22 0x0000000100cb4094 in expand_all_functions () at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/cgraphunit.cc:2028
#23 0x0000000100cb5148 in symbol_table::compile (this=0x7ffff5480000) at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/cgraphunit.cc:2404
#24 0x0000000100cb596c in symbol_table::finalize_compilation_unit
(this=0x7ffff5480000) at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/cgraphunit.cc:2589
#25 0x0000000101809178 in compile_file () at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/toplev.cc:476
#26 0x000000010180e000 in do_compile () at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/toplev.cc:2158
#27 0x000000010180e690 in toplev::main (this=0x7fffffffeb52, argc=11,
argv=0x7fffffffefa8) at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/toplev.cc:2314
#28 0x0000000102fb4674 in main (argc=11, argv=0x7fffffffefa8) at
/usr/src/debug/cross-alpha-unknown-linux-gnu/gcc-14.1.1_p20240518/gcc-14-20240518/gcc/main.cc:39

[Bug rtl-optimization/115297] [14/15 regression] alpha: ICE in simplify_subreg, at simplify-rtx.cc:7554 with -O1

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115297

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[14 regression] alpha: ICE  |[14/15 regression] alpha:
                   |in simplify_subreg, at      |ICE in simplify_subreg, at
                   |simplify-rtx.cc:7554 with   |simplify-rtx.cc:7554 with
                   |-O1                         |-O1
   Target Milestone|---                         |14.2

[Bug rtl-optimization/115297] [14/15 regression] alpha: ICE in simplify_subreg, at simplify-rtx.cc:7554 with -O1

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115297

--- Comment #1 from Uroš Bizjak <ubizjak at gmail dot com> ---
Created attachment 58315
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58315&action=edit
Proposed patch

any_divmod instructions are modelled with invalid RTX:

  [(set (match_operand:DI 0 "register_operand" "=c")
        (sign_extend:DI (match_operator:SI 3 "divmod_operator"
                        [(match_operand:DI 1 "register_operand" "a")
                         (match_operand:DI 2 "register_operand" "b")])))
   (clobber (reg:DI 23))
   (clobber (reg:DI 28))]

SImode divmod_operator (div,mod,udiv,umod) has DImode operands.

The patch adds truncate:SI to the input operand to make machine modes
consistent.

[Bug rtl-optimization/115297] [14/15 regression] alpha: ICE in simplify_subreg, at simplify-rtx.cc:7554 with -O1

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115297

--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:0ac802064c2a018cf166c37841697e867de65a95

commit r15-943-g0ac802064c2a018cf166c37841697e867de65a95
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri May 31 15:52:03 2024 +0200

    alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]

    any_divmod instructions are modelled with invalid RTX:

      [(set (match_operand:DI 0 "register_operand" "=c")
            (sign_extend:DI (match_operator:SI 3 "divmod_operator"
                            [(match_operand:DI 1 "register_operand" "a")
                             (match_operand:DI 2 "register_operand" "b")])))
       (clobber (reg:DI 23))
       (clobber (reg:DI 28))]

    where SImode divmod_operator (div,mod,udiv,umod) has DImode operands.

    Wrap input operand with truncate:SI to make machine modes consistent.

            PR target/115297

    gcc/ChangeLog:

            * config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode
            operands 3 and 4 with truncate:SI RTX.
            (*divmodsi_internal_er): Ditto for operands 1 and 2.
            (*divmodsi_internal_er_1): Ditto.
            (*divmodsi_internal): Ditto.
            * config/alpha/constraints.md ("b"): Correct register
            number in the description.

    gcc/testsuite/ChangeLog:

            * gcc.target/alpha/pr115297.c: New test.

[Bug rtl-optimization/115297] [14/15 regression] alpha: ICE in simplify_subreg, at simplify-rtx.cc:7554 with -O1

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115297

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-14 branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:ec92744de552303a1424085203e1311bd9146f21

commit r14-10264-gec92744de552303a1424085203e1311bd9146f21
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri May 31 15:52:03 2024 +0200

    alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]

    any_divmod instructions are modelled with invalid RTX:

      [(set (match_operand:DI 0 "register_operand" "=c")
            (sign_extend:DI (match_operator:SI 3 "divmod_operator"
                            [(match_operand:DI 1 "register_operand" "a")
                             (match_operand:DI 2 "register_operand" "b")])))
       (clobber (reg:DI 23))
       (clobber (reg:DI 28))]

    where SImode divmod_operator (div,mod,udiv,umod) has DImode operands.

    Wrap input operand with truncate:SI to make machine modes consistent.

            PR target/115297

    gcc/ChangeLog:

            * config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode
            operands 3 and 4 with truncate:SI RTX.
            (*divmodsi_internal_er): Ditto for operands 1 and 2.
            (*divmodsi_internal_er_1): Ditto.
            (*divmodsi_internal): Ditto.
            * config/alpha/constraints.md ("b"): Correct register
            number in the description.

    gcc/testsuite/ChangeLog:

            * gcc.target/alpha/pr115297.c: New test.

    (cherry picked from commit 0ac802064c2a018cf166c37841697e867de65a95)

[Bug rtl-optimization/115297] [14/15 regression] alpha: ICE in simplify_subreg, at simplify-rtx.cc:7554 with -O1

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115297

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-13 branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:ed06ca80bae174f1179222ff8e6b93464006e86a

commit r13-8820-ged06ca80bae174f1179222ff8e6b93464006e86a
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri May 31 15:52:03 2024 +0200

    alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]

    any_divmod instructions are modelled with invalid RTX:

      [(set (match_operand:DI 0 "register_operand" "=c")
            (sign_extend:DI (match_operator:SI 3 "divmod_operator"
                            [(match_operand:DI 1 "register_operand" "a")
                             (match_operand:DI 2 "register_operand" "b")])))
       (clobber (reg:DI 23))
       (clobber (reg:DI 28))]

    where SImode divmod_operator (div,mod,udiv,umod) has DImode operands.

    Wrap input operand with truncate:SI to make machine modes consistent.

            PR target/115297

    gcc/ChangeLog:

            * config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode
            operands 3 and 4 with truncate:SI RTX.
            (*divmodsi_internal_er): Ditto for operands 1 and 2.
            (*divmodsi_internal_er_1): Ditto.
            (*divmodsi_internal): Ditto.
            * config/alpha/constraints.md ("b"): Correct register
            number in the description.

    gcc/testsuite/ChangeLog:

            * gcc.target/alpha/pr115297.c: New test.

    (cherry picked from commit 0ac802064c2a018cf166c37841697e867de65a95)

[Bug rtl-optimization/115297] [14/15 regression] alpha: ICE in simplify_subreg, at simplify-rtx.cc:7554 with -O1

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115297

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-12 branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:c6c2a6cebabc5f78cef3d81cedb4b3b578478b9f

commit r12-10486-gc6c2a6cebabc5f78cef3d81cedb4b3b578478b9f
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri May 31 15:52:03 2024 +0200

    alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]

    any_divmod instructions are modelled with invalid RTX:

      [(set (match_operand:DI 0 "register_operand" "=c")
            (sign_extend:DI (match_operator:SI 3 "divmod_operator"
                            [(match_operand:DI 1 "register_operand" "a")
                             (match_operand:DI 2 "register_operand" "b")])))
       (clobber (reg:DI 23))
       (clobber (reg:DI 28))]

    where SImode divmod_operator (div,mod,udiv,umod) has DImode operands.

    Wrap input operand with truncate:SI to make machine modes consistent.

            PR target/115297

    gcc/ChangeLog:

            * config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode
            operands 3 and 4 with truncate:SI RTX.
            (*divmodsi_internal_er): Ditto for operands 1 and 2.
            (*divmodsi_internal_er_1): Ditto.
            (*divmodsi_internal): Ditto.
            * config/alpha/constraints.md ("b"): Correct register
            number in the description.

    gcc/testsuite/ChangeLog:

            * gcc.target/alpha/pr115297.c: New test.

    (cherry picked from commit 0ac802064c2a018cf166c37841697e867de65a95)

[Bug rtl-optimization/115297] [14/15 regression] alpha: ICE in simplify_subreg, at simplify-rtx.cc:7554 with -O1

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115297

--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-11 branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:835b913aff1b1a813df3b9d2bbef170ae7d8856d

commit r11-11463-g835b913aff1b1a813df3b9d2bbef170ae7d8856d
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri May 31 15:52:03 2024 +0200

    alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]

    any_divmod instructions are modelled with invalid RTX:

      [(set (match_operand:DI 0 "register_operand" "=c")
            (sign_extend:DI (match_operator:SI 3 "divmod_operator"
                            [(match_operand:DI 1 "register_operand" "a")
                             (match_operand:DI 2 "register_operand" "b")])))
       (clobber (reg:DI 23))
       (clobber (reg:DI 28))]

    where SImode divmod_operator (div,mod,udiv,umod) has DImode operands.

    Wrap input operand with truncate:SI to make machine modes consistent.

            PR target/115297

    gcc/ChangeLog:

            * config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode
            operands 3 and 4 with truncate:SI RTX.
            (*divmodsi_internal_er): Ditto for operands 1 and 2.
            (*divmodsi_internal_er_1): Ditto.
            (*divmodsi_internal): Ditto.
            * config/alpha/constraints.md ("b"): Correct register
            number in the description.

    gcc/testsuite/ChangeLog:

            * gcc.target/alpha/pr115297.c: New test.

    (cherry picked from commit 0ac802064c2a018cf166c37841697e867de65a95)

[Bug rtl-optimization/115297] [14/15 regression] alpha: ICE in simplify_subreg, at simplify-rtx.cc:7554 with -O1

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115297

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |ubizjak at gmail dot com
             Status|UNCONFIRMED                 |RESOLVED
   Target Milestone|14.2                        |11.5
         Resolution|---                         |FIXED

--- Comment #7 from Uroš Bizjak <ubizjak at gmail dot com> ---
Fixed everywhere.