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From: "rdapp at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug tree-optimization/115382] Wrong code with in-order conditional
 reduction and masked loops
Date: Fri, 07 Jun 2024 19:02:16 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: tree-optimization
X-Bugzilla-Version: 15.0
X-Bugzilla-Keywords: wrong-code
X-Bugzilla-Severity: normal
X-Bugzilla-Who: rdapp at gcc dot gnu.org
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Message-ID: <bug-115382-4-f0Zt5Rag86@http.gcc.gnu.org/bugzilla/>
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D115382

--- Comment #1 from Robin Dapp <rdapp at gcc dot gnu.org> ---
Would something like this work?  The testcase ran successfully with Intel's=
 SME
with that change (and aarch64 qemu with SVE).

diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index 028692614bb..f9bf6a45611 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -7215,7 +7215,21 @@ vectorize_fold_left_reduction (loop_vec_info loop_vi=
nfo,
       tree len =3D NULL_TREE;
       tree bias =3D NULL_TREE;
       if (LOOP_VINFO_FULLY_MASKED_P (loop_vinfo))
-       mask =3D vect_get_loop_mask (loop_vinfo, gsi, masks, vec_num, vecty=
pe_in,
i);
+       {
+         tree mask_loop =3D vect_get_loop_mask (loop_vinfo, gsi, masks,
+                                              vec_num, vectype_in, i);
+         if (is_cond_op)
+           {
+             /* Merge the loop mask and the cond_op mask.  */
+             mask =3D make_ssa_name (TREE_TYPE (mask_loop));
+             gassign *and_stmt =3D gimple_build_assign (mask, BIT_AND_EXPR,
+                                                      mask_loop,
+                                                      vec_opmask[i]);
+             gsi_insert_before (gsi, and_stmt, GSI_SAME_STMT);
+           }
+         else
+           mask =3D mask_loop;
+       }
       else if (is_cond_op)
        mask =3D vec_opmask[i];
       if (LOOP_VINFO_FULLY_WITH_LENGTH_P (loop_vinfo))
--=20
2.45.1=