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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/115456] RISC-V: ICE: unrecognizable insn with
 march=rv64gcv_zvfhmin
Date: Fri, 14 Jun 2024 07:56:01 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D115456

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:c2c61d8902dbda017b1647252d17bce141493433

commit r15-1327-gc2c61d8902dbda017b1647252d17bce141493433
Author: Pan Li <pan2.li@intel.com>
Date:   Fri Jun 14 14:54:22 2024 +0800

    RISC-V: Bugfix vec_extract v mode iterator restriction mismatch

    We have vec_extract pattern which takes ZVFHMIN as the mode
    iterator of the V mode.  Aka VF_ZVFHMIN iterator.  But it will
    expand to pred_extract_first pattern which takes the ZVFH as the mode
    iterator of the V mode.  AKa VF.  The mismatch will result in one ICE
    similar as below:

    insn 30 29 31 2 (set (reg:HF 156 [ _2 ])
            (unspec:HF [
                    (vec_select:HF (reg:RVVMF2HF 134 [ _1 ])
                        (parallel [
                                (const_int 0 [0])
                            ]))
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)) "compress_run-2.c":22:3 -1
         (nil))
    during RTL pass: vregs
    compress_run-2.c:25:1: internal compiler error: in extract_insn, at
    recog.cc:2812
    0xb3bc47 _fatal_insn(char const*, rtx_def const*, char const*, int, char
    const*)
            ../../../gcc/gcc/rtl-error.cc:108
    0xb3bc69 _fatal_insn_not_found(rtx_def const*, char const*, int, char
    const*)
            ../../../gcc/gcc/rtl-error.cc:116
    0xb3a545 extract_insn(rtx_insn*)
            ../../../gcc/gcc/recog.cc:2812
    0x1010e9e instantiate_virtual_regs_in_insn
            ../../../gcc/gcc/function.cc:1612
    0x1010e9e instantiate_virtual_regs
            ../../../gcc/gcc/function.cc:1995
    0x1010e9e execute
            ../../../gcc/gcc/function.cc:2042

    The below test suites are passed for this patch.
    1. The rv64gcv fully regression test.
    2. The rv64gcv build with glibc.

    There may be other similar issue(s) for the mismatch,  we will take care
    of them by test cases one by one.

            PR target/115456

    gcc/ChangeLog:

            * config/riscv/vector-iterators.md: Leverage V_ZVFH instead of V
            which contains the VF_ZVFHMIN for alignment.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr115456-2.c: New test.
            * gcc.target/riscv/rvv/base/pr115456-3.c: New test.

    Signed-off-by: Pan Li <pan2.li@intel.com>=