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From: "pan2.li at intel dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin Date: Thu, 13 Jun 2024 04:32:49 +0000 [thread overview] Message-ID: <bug-115456-4-fwnv7gEC8Y@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-115456-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456 --- Comment #2 from Li Pan <pan2.li at intel dot com> --- According to the ISA, Zvfhmin only contains 2 insns, quote as below " The Zvfhmin extension provides minimal support for vectors of IEEE 754-2008 binary16 values, adding conversions to and from binary32. When the Zvfhmin extension is implemented, the vfwcvt.f.f.v and vfncvt.f.f.w instructions become defined when SEW=16. The EEW=16 floating-point operands of these instructions use the binary16 format. " Thus, for this case the vfmv.f.s should be invalid for V4HF mode but expanded. We should not generate insn like that here when only zvfhmin is given.
next prev parent reply other threads:[~2024-06-13 4:32 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-06-12 7:48 [Bug c/115456] New: " sh.chiang04 at gmail dot com 2024-06-12 14:46 ` [Bug target/115456] RISC-V: " pan2.li at intel dot com 2024-06-13 4:32 ` pan2.li at intel dot com [this message] 2024-06-13 9:46 ` cvs-commit at gcc dot gnu.org 2024-06-13 13:30 ` sh.chiang04 at gmail dot com 2024-06-14 7:56 ` cvs-commit at gcc dot gnu.org
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