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From: "pan2.li at intel dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/115456] RISC-V: ICE: unrecognizable insn with
 march=rv64gcv_zvfhmin
Date: Thu, 13 Jun 2024 04:32:49 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D115456

--- Comment #2 from Li Pan <pan2.li at intel dot com> ---
According to the ISA, Zvfhmin only contains 2 insns, quote as below

"
The Zvfhmin extension provides minimal support for vectors of IEEE 754-2008
binary16 values, adding conversions to and from binary32. When the Zvfhmin
extension is implemented, the vfwcvt.f.f.v and vfncvt.f.f.w instructions be=
come
defined when SEW=3D16. The EEW=3D16 floating-point operands of these instru=
ctions
use the binary16 format.
"

Thus, for this case the vfmv.f.s should be invalid for V4HF mode but expand=
ed.

We should not generate insn like that here when only zvfhmin is given.=