[Bug c/115456] New: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

[Bug c/115456] New: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

[sh.chiang04 at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456

            Bug ID: 115456
           Summary: ICE: unrecognizable insn with march=rv64gcv_zvfhmin
           Product: gcc
           Version: 14.1.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: sh.chiang04 at gmail dot com
  Target Milestone: ---
            Target: riscv64*-*-*

The fail test is extract from
gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c


compile option: 
  -march=rv64gcv_zvfhmin -mabi=lp64d -ftree-vectorize -O3 -mrvv-max-lmul=m1
-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math

test case:

#include <assert.h>
#include <stdint-gcc.h>

typedef _Float16 vnx4f __attribute__ ((vector_size (8)));

vnx4f __attribute__ ((noinline, noclone))
test_5 (vnx4f x, vnx4f y)
{
  return __builtin_shufflevector (x, y, 1, 3, 6, 7);
}

int
main (void)
{
  vnx4f test_5_x = {0, 1, 3, 4};
  vnx4f test_5_y = {4, 5, 6, 7};
  vnx4f test_5_except = {1, 4, 6, 7};
  vnx4f test_5_real;
  test_5_real = test_5 (test_5_x, test_5_y);
  for (int i = 0; i < 4; i++)
    assert (test_5_real[i] == test_5_except[i]);

  return 0;
}

error message:

compress_run-2.c:27:1: error: unrecognizable insn:
   27 | }
      | ^
(insn 19 18 20 2 (set (reg:HF 150 [ _13 ])
        (unspec:HF [
                (vec_select:HF (reg:V4HF 134 [ _1 ])
                    (parallel [
                            (const_int 0 [0])
                        ]))
                (reg:SI 67 vtype)
            ] UNSPEC_VPREDICATE)) "compress_run-2.c":24:5 -1
     (nil))
during RTL pass: vregs
compress_run-2.c:27:1: internal compiler error: in extract_insn, at
recog.cc:2812
0x1a627ef _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        ../../../gcc/gcc/rtl-error.cc:108
0x1a62834 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        ../../../gcc/gcc/rtl-error.cc:116
0x1a0f356 extract_insn(rtx_insn*)
        ../../../gcc/gcc/recog.cc:2812
0x159ee61 instantiate_virtual_regs_in_insn
        ../../../gcc/gcc/function.cc:1612
0x15a04aa instantiate_virtual_regs
        ../../../gcc/gcc/function.cc:1995
0x15a058e execute
        ../../../gcc/gcc/function.cc:2042

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456

--- Comment #1 from Li Pan <pan2.li at intel dot com> ---
Ack, will take care of it.

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456

--- Comment #2 from Li Pan <pan2.li at intel dot com> ---
According to the ISA, Zvfhmin only contains 2 insns, quote as below

"
The Zvfhmin extension provides minimal support for vectors of IEEE 754-2008
binary16 values, adding conversions to and from binary32. When the Zvfhmin
extension is implemented, the vfwcvt.f.f.v and vfncvt.f.f.w instructions become
defined when SEW=16. The EEW=16 floating-point operands of these instructions
use the binary16 format.
"

Thus, for this case the vfmv.f.s should be invalid for V4HF mode but expanded.

We should not generate insn like that here when only zvfhmin is given.

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:3dac1049c1211e6d06c2536b86445a6334c3866d

commit r15-1243-g3dac1049c1211e6d06c2536b86445a6334c3866d
Author: Pan Li <pan2.li@intel.com>
Date:   Thu Jun 13 15:26:59 2024 +0800

    RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch

    We have vec_extract pattern which takes ZVFHMIN as the mode
    iterator of the VLS mode.  Aka V_VLS.  But it will expand to
    pred_extract_first pattern which takes the ZVFH as the mode
    iterator of the VLS mode.  AKa V_VLSF.  The mismatch will
    result in one ICE similar as below:

    error: unrecognizable insn:
       27 | }
          | ^
    (insn 19 18 20 2 (set (reg:HF 150 [ _13 ])
            (unspec:HF [
                    (vec_select:HF (reg:V4HF 134 [ _1 ])
                        (parallel [
                                (const_int 0 [0])
                            ]))
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)) "compress_run-2.c":24:5 -1
         (nil))
    during RTL pass: vregs
    compress_run-2.c:27:1: internal compiler error: in extract_insn, at
    recog.cc:2812
    0x1a627ef _fatal_insn(char const*, rtx_def const*, char const*, int,
    char const*)
            ../../../gcc/gcc/rtl-error.cc:108
    0x1a62834 _fatal_insn_not_found(rtx_def const*, char const*, int, char
    const*)
            ../../../gcc/gcc/rtl-error.cc:116
    0x1a0f356 extract_insn(rtx_insn*)
            ../../../gcc/gcc/recog.cc:2812
    0x159ee61 instantiate_virtual_regs_in_insn
            ../../../gcc/gcc/function.cc:1612
    0x15a04aa instantiate_virtual_regs
            ../../../gcc/gcc/function.cc:1995
    0x15a058e execute
            ../../../gcc/gcc/function.cc:2042

    This patch would like to fix this issue by align the mode
    iterator restriction to ZVFH.

    The below test suites are passed for this patch.
    1. The rv64gcv fully regression test.
    2. The rv64gcv build with glibc.

            PR target/115456

    gcc/ChangeLog:

            * config/riscv/autovec.md: Take ZVFH mode iterator instead of
            the ZVFHMIN for the alignment.
            * config/riscv/vector-iterators.md: Add 2 new iterator
            V_VLS_ZVFH and VLS_ZVFH.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr115456-1.c: New test.

    Signed-off-by: Pan Li <pan2.li@intel.com>

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

[sh.chiang04 at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456

--- Comment #4 from Monk Chiang <sh.chiang04 at gmail dot com> ---
The test case, if add this option: -mrvv-vector-bits=zvl
It has a new internal compiler error.

compress_run-2.c:25:1: error: unrecognizable insn:
   25 | }
      | ^
(insn 30 29 31 2 (set (reg:HF 156 [ _2 ])
        (unspec:HF [
                (vec_select:HF (reg:RVVMF2HF 134 [ _1 ])
                    (parallel [
                            (const_int 0 [0])
                        ]))
                (reg:SI 67 vtype)
            ] UNSPEC_VPREDICATE)) "compress_run-2.c":22:3 -1
     (nil))
during RTL pass: vregs
compress_run-2.c:25:1: internal compiler error: in extract_insn, at
recog.cc:2812
0xb3bc47 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        ../../../gcc/gcc/rtl-error.cc:108
0xb3bc69 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        ../../../gcc/gcc/rtl-error.cc:116
0xb3a545 extract_insn(rtx_insn*)
        ../../../gcc/gcc/recog.cc:2812
0x1010e9e instantiate_virtual_regs_in_insn
        ../../../gcc/gcc/function.cc:1612
0x1010e9e instantiate_virtual_regs
        ../../../gcc/gcc/function.cc:1995
0x1010e9e execute
        ../../../gcc/gcc/function.cc:2042

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:c2c61d8902dbda017b1647252d17bce141493433

commit r15-1327-gc2c61d8902dbda017b1647252d17bce141493433
Author: Pan Li <pan2.li@intel.com>
Date:   Fri Jun 14 14:54:22 2024 +0800

    RISC-V: Bugfix vec_extract v mode iterator restriction mismatch

    We have vec_extract pattern which takes ZVFHMIN as the mode
    iterator of the V mode.  Aka VF_ZVFHMIN iterator.  But it will
    expand to pred_extract_first pattern which takes the ZVFH as the mode
    iterator of the V mode.  AKa VF.  The mismatch will result in one ICE
    similar as below:

    insn 30 29 31 2 (set (reg:HF 156 [ _2 ])
            (unspec:HF [
                    (vec_select:HF (reg:RVVMF2HF 134 [ _1 ])
                        (parallel [
                                (const_int 0 [0])
                            ]))
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)) "compress_run-2.c":22:3 -1
         (nil))
    during RTL pass: vregs
    compress_run-2.c:25:1: internal compiler error: in extract_insn, at
    recog.cc:2812
    0xb3bc47 _fatal_insn(char const*, rtx_def const*, char const*, int, char
    const*)
            ../../../gcc/gcc/rtl-error.cc:108
    0xb3bc69 _fatal_insn_not_found(rtx_def const*, char const*, int, char
    const*)
            ../../../gcc/gcc/rtl-error.cc:116
    0xb3a545 extract_insn(rtx_insn*)
            ../../../gcc/gcc/recog.cc:2812
    0x1010e9e instantiate_virtual_regs_in_insn
            ../../../gcc/gcc/function.cc:1612
    0x1010e9e instantiate_virtual_regs
            ../../../gcc/gcc/function.cc:1995
    0x1010e9e execute
            ../../../gcc/gcc/function.cc:2042

    The below test suites are passed for this patch.
    1. The rv64gcv fully regression test.
    2. The rv64gcv build with glibc.

    There may be other similar issue(s) for the mismatch,  we will take care
    of them by test cases one by one.

            PR target/115456

    gcc/ChangeLog:

            * config/riscv/vector-iterators.md: Leverage V_ZVFH instead of V
            which contains the VF_ZVFHMIN for alignment.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr115456-2.c: New test.
            * gcc.target/riscv/rvv/base/pr115456-3.c: New test.

    Signed-off-by: Pan Li <pan2.li@intel.com>