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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/115487] -march=cascadelake causes spilling
Date: Fri, 14 Jun 2024 09:59:04 +0000	[thread overview]
Message-ID: <bug-115487-4-xelAQIS5Ry@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-115487-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115487

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
Building chain #7...
  Adding insn 34 to chain #7
  r133 def in insn 33 isn't convertible
  Mark r133 def in insn 33 as requiring both modes in chain #7
Collected chain #7...
  insns: 34
  defs to convert: r133
Computing gain for chain #7...
  Instruction gain 8 for    34: [r103:SI]=r133:DI
  Instruction conversion gain: 8
  Registers conversion cost: 6
  Total gain: 2
Converting chain #7...
deferring rescan insn with uid = 89.
deferring rescan insn with uid = 90.
deferring rescan insn with uid = 91.
  Copied r133 to a vector register r141 for insn 33

the question is why we start the chain at

   33: r133:DI=vec_select(r131:V4SI#0,parallel)

rather than at

   28: r131:V4SI=[r102:SI]

or why we are working with SImode regs/vectors in the lowering.  The code
before STV2 looks perfectly OK, and most definitely the costs are totally
off here.

      parent reply	other threads:[~2024-06-14  9:59 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-14  9:31 [Bug target/115487] New: " rguenth at gcc dot gnu.org
2024-06-14  9:42 ` [Bug target/115487] " rguenth at gcc dot gnu.org
2024-06-14  9:59 ` rguenth at gcc dot gnu.org [this message]

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