* [Bug target/115519] s390 fallout from removing vcond{,u,eq} patterns
2024-06-17 9:05 [Bug target/115519] New: s390 fallout from removing vcond{,u,eq} patterns stefansf at gcc dot gnu.org
@ 2024-06-18 6:49 ` stefansf at gcc dot gnu.org
2024-06-24 8:53 ` stefansf at gcc dot gnu.org
2024-06-24 11:52 ` stefansf at gcc dot gnu.org
2 siblings, 0 replies; 4+ messages in thread
From: stefansf at gcc dot gnu.org @ 2024-06-18 6:49 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115519
--- Comment #1 from Stefan Schulze Frielinghaus <stefansf at gcc dot gnu.org> ---
For example, for function vesrlf_ge from vcond-shift.c we do not end up with
vl %v2,0(%r2),3
vl %v0,16(%r2),3
lgr %r1,%r2
vesrlf %v4,%v2,31
vesrlf %v6,%v0,31
vst %v4,0(%r1),3
vst %v6,16(%r1),3
br %r14
anymore but
vl %v0,0(%r2),3
vl %v4,16(%r2),3
vgmf %v6,31,31
vzero %v2
vesraf %v1,%v0,31
vesraf %v3,%v4,31
vsel %v5,%v6,%v2,%v1
vsel %v7,%v6,%v2,%v3
lgr %r1,%r2
vst %v5,0(%r1),3
vst %v7,16(%r1),3
br %r14
During a vcond expand we optimized x < 0 ? 1 : 0 into x >> 31 which we fail to
do, now. Doing it late in combine fails, too, since we never come up with a
combination of insn 7, 8, 9, and 10:
(insn 7 6 8 2 (set (reg:V4SI 69 [ mask__5.8_4 ])
(ashiftrt:V4SI (reg:V4SI 68 [ MEM <vector(4) int> [(int *)xx_10] ])
(const_int 31 [0x1f]))) "vcond-shift.c":155:28 905 {*ashrv4si3}
(expr_list:REG_DEAD (reg:V4SI 68 [ MEM <vector(4) int> [(int *)xx_10] ])
(nil)))
(insn 8 7 9 2 (set (reg:V4SI 70)
(const_vector:V4SI [
(const_int 1 [0x1]) repeated x4
])) 410 {movv4si}
(nil))
(insn 9 8 10 2 (set (reg:V4SI 71)
(const_vector:V4SI [
(const_int 0 [0]) repeated x4
])) 410 {movv4si}
(nil))
(insn 10 9 11 2 (set (reg:V4SI 62 [ vect_patt_18.9 ])
(if_then_else:V4SI (eq (reg:V4SI 69 [ mask__5.8_4 ])
(const_vector:V4SI [
(const_int 0 [0]) repeated x4
]))
(reg:V4SI 71)
(reg:V4SI 70))) 1265 {*vec_sel0v4si}
(expr_list:REG_DEAD (reg:V4SI 69 [ mask__5.8_4 ])
(expr_list:REG_EQUAL (if_then_else:V4SI (eq (reg:V4SI 69 [ mask__5.8_4
])
(const_vector:V4SI [
(const_int 0 [0]) repeated x4
]))
(const_vector:V4SI [
(const_int 0 [0]) repeated x4
])
(const_vector:V4SI [
(const_int 1 [0x1]) repeated x4
]))
(nil))))
So maybe this is something for match.pd?
^ permalink raw reply [flat|nested] 4+ messages in thread* [Bug target/115519] s390 fallout from removing vcond{,u,eq} patterns
2024-06-17 9:05 [Bug target/115519] New: s390 fallout from removing vcond{,u,eq} patterns stefansf at gcc dot gnu.org
2024-06-18 6:49 ` [Bug target/115519] " stefansf at gcc dot gnu.org
@ 2024-06-24 8:53 ` stefansf at gcc dot gnu.org
2024-06-24 11:52 ` stefansf at gcc dot gnu.org
2 siblings, 0 replies; 4+ messages in thread
From: stefansf at gcc dot gnu.org @ 2024-06-24 8:53 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115519
--- Comment #2 from Stefan Schulze Frielinghaus <stefansf at gcc dot gnu.org> ---
Just saw on the ML that a match.pd fix already exists
https://gcc.gnu.org/pipermail/gcc-patches/2024-June/655484.html
A quick test shows that this fixes vcond-shift.c where we now emit
((int) ((unsigned int) xx >> 31) + xx) >> 1
and previously
(xx - (xx >> 31)) >> 1
which is basically the same. We just have to adapt the times for
scan-assembler w.r.t. signed/unsigned shifts:
diff --git a/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c
b/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c
index a6b4e97aa50..b942f44039d 100644
--- a/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c
+++ b/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c
@@ -3,13 +3,13 @@
/* { dg-do compile { target { s390*-*-* } } } */
/* { dg-options "-O3 -march=z13 -mzarch" } */
-/* { dg-final { scan-assembler-times "vesraf\t%v.?,%v.?,31" 6 } } */
-/* { dg-final { scan-assembler-times "vesrah\t%v.?,%v.?,15" 6 } } */
-/* { dg-final { scan-assembler-times "vesrab\t%v.?,%v.?,7" 6 } } */
+/* { dg-final { scan-assembler-times "vesraf\t%v.?,%v.?,31" 4 } } */
+/* { dg-final { scan-assembler-times "vesrah\t%v.?,%v.?,15" 4 } } */
+/* { dg-final { scan-assembler-times "vesrab\t%v.?,%v.?,7" 4 } } */
/* { dg-final { scan-assembler-not "vzero\t*" } } */
-/* { dg-final { scan-assembler-times "vesrlf\t%v.?,%v.?,31" 4 } } */
-/* { dg-final { scan-assembler-times "vesrlh\t%v.?,%v.?,15" 4 } } */
-/* { dg-final { scan-assembler-times "vesrlb\t%v.?,%v.?,7" 4 } } */
+/* { dg-final { scan-assembler-times "vesrlf\t%v.?,%v.?,31" 6 } } */
+/* { dg-final { scan-assembler-times "vesrlh\t%v.?,%v.?,15" 6 } } */
+/* { dg-final { scan-assembler-times "vesrlb\t%v.?,%v.?,7" 6 } } */
/* Make it expand to two vector operations. */
#define ITER(X) (2 * (16 / sizeof (X[1])))
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