From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id E1C3C3858CD9; Mon, 24 Jun 2024 08:53:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E1C3C3858CD9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1719219216; bh=ODJRnuHSHLTOpeU8ijdMII15z8MIN4W5JrQ/Xqgd0XE=; h=From:To:Subject:Date:In-Reply-To:References:From; b=cQlEE40bpLivOzcFqPnvGe+HGbvG9zn0TiEJz0PntS4ZS4ifj7DVagiV6vfker0/E RPh4IolERxTEHOepCdOf9umRUW5Co5l9ZtiEMaU2UeXcJ919mFL6DutcFfuKknlYDZ PKZILnxtlHOFgfn+PGx9LC5ZEAz+f1JLrYATnmyA= From: "stefansf at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/115519] s390 fallout from removing vcond{,u,eq} patterns Date: Mon, 24 Jun 2024 08:53:35 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: unknown X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: stefansf at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D115519 --- Comment #2 from Stefan Schulze Frielinghaus --- Just saw on the ML that a match.pd fix already exists https://gcc.gnu.org/pipermail/gcc-patches/2024-June/655484.html A quick test shows that this fixes vcond-shift.c where we now emit ((int) ((unsigned int) xx >> 31) + xx) >> 1 and previously (xx - (xx >> 31)) >> 1 which is basically the same. We just have to adapt the times for scan-assembler w.r.t. signed/unsigned shifts: diff --git a/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c b/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c index a6b4e97aa50..b942f44039d 100644 --- a/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c +++ b/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c @@ -3,13 +3,13 @@ /* { dg-do compile { target { s390*-*-* } } } */ /* { dg-options "-O3 -march=3Dz13 -mzarch" } */ -/* { dg-final { scan-assembler-times "vesraf\t%v.?,%v.?,31" 6 } } */ -/* { dg-final { scan-assembler-times "vesrah\t%v.?,%v.?,15" 6 } } */ -/* { dg-final { scan-assembler-times "vesrab\t%v.?,%v.?,7" 6 } } */ +/* { dg-final { scan-assembler-times "vesraf\t%v.?,%v.?,31" 4 } } */ +/* { dg-final { scan-assembler-times "vesrah\t%v.?,%v.?,15" 4 } } */ +/* { dg-final { scan-assembler-times "vesrab\t%v.?,%v.?,7" 4 } } */ /* { dg-final { scan-assembler-not "vzero\t*" } } */ -/* { dg-final { scan-assembler-times "vesrlf\t%v.?,%v.?,31" 4 } } */ -/* { dg-final { scan-assembler-times "vesrlh\t%v.?,%v.?,15" 4 } } */ -/* { dg-final { scan-assembler-times "vesrlb\t%v.?,%v.?,7" 4 } } */ +/* { dg-final { scan-assembler-times "vesrlf\t%v.?,%v.?,31" 6 } } */ +/* { dg-final { scan-assembler-times "vesrlh\t%v.?,%v.?,15" 6 } } */ +/* { dg-final { scan-assembler-times "vesrlb\t%v.?,%v.?,7" 6 } } */ /* Make it expand to two vector operations. */ #define ITER(X) (2 * (16 / sizeof (X[1])))=