[Bug target/115687] RISC-V optimization when "lui" instructions can be merged

["palmer at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115687

--- Comment #8 from Palmer Dabbelt <palmer at gcc dot gnu.org> ---
(In reply to Andrew Waterman from comment #6)
> I note MIPS sets TARGET_CONST_ANCHOR to 0x8000, and that architecture's
> ADDIU instruction has a 16-bit immediate.  RISC-V's ADDI instruction has a
> 12-bit immediate, so presumably we should be setting it to 0x800.

Ya, sorry, I wasn't paying attention -- regardless I think Vineet's on the
right track here with the splitter messing with us here, the incoming code has
a constant anchor already so dealing with those is sort of a different problem.

If removing that splitter is on the TODO list that seems reasonable, though I'd
taken a very different approach and just hacked up a post-split CSE as it seems
like we could end up in more situations like this.  I have no idea if that's a
sane idea, I sent an RFC to the lists to see what people think...