[Bug other/115687] New: RISC-V optimization when "lui" instructions can be merged

["Explorer09 at gmail dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115687

            Bug ID: 115687
           Summary: RISC-V optimization when "lui" instructions can be
                    merged
           Product: gcc
           Version: 14.1.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: other
          Assignee: unassigned at gcc dot gnu.org
          Reporter: Explorer09 at gmail dot com
  Target Milestone: ---

```c
#include <stdio.h>
int main() {
    unsigned int a = 0x4010; // (0x4 << 12) + 0x10
    unsigned int b = 0x4020; // (0x4 << 12) + 0x20
    unsigned int c = 0x3FF0; // (0x4 << 12) - 0x10
    printf("0x%08x 0x%08x 0x%08x\n", a, b, c);
    return 0;
}
```

RISC-V (64-bits) GCC 14.1 with -Os option produces:

```text
    li a3,16384
    li a2,16384
    li a1,16384
    lui a0,%hi(.LC0)
    addi sp,sp,-16
    addi a3,a3,-16
    addi a2,a2,32
    addi a1,a1,16
    addi a0,a0,%lo(.LC0)
    sd ra,8(sp)
    call printf
    ld ra,8(sp)
    li a0,0
    addi sp,sp,16
    jr ra
```

There are three "li ...,16384" instructions generated, while it is possible to
reduce them to one. For example, by using the same "a1" register for the
addends:

```text
    li a1,16384
    ...
    addi a3,a1,-16
    addi a2,a1,32
    addi a1,a1,16
```