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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/115862] [15 Regression] RISC-V: ICE during RTL
 combine pass in malloc.c for zvl512b and zvl1024b
Date: Thu, 11 Jul 2024 04:40:28 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D115862

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[15] RISC-V: ICE during RTL |[15 Regression] RISC-V: ICE
                   |combine pass in malloc.c    |during RTL combine pass in
                   |for zvl512b and zvl1024b    |malloc.c for zvl512b and
                   |                            |zvl1024b
   Target Milestone|---                         |15.0
          Component|target                      |rtl-optimization

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Trying 21 -> 29:
   21: r149:DI=3Dr139:V8SI#0 0>>0x20
   29: [r136:DI+0x4]=3Dr149:DI#0
      REG_DEAD r149:DI


(insn 21 20 29 2 (set (reg:DI 149)
        (lshiftrt:DI (subreg:DI (reg:V8SI 139 [ vect__2.14_29 ]) 0)
            (const_int 32 [0x20]))) "/app/example.cpp":36:12 299 {lshrdi3}
     (nil))
(insn 29 21 30 2 (set (mem/c:SI (plus:DI (reg/f:DI 136 [ .result_ptrD.2808 =
])
                (const_int 4 [0x4])) [3 MEM <vector(8) intD.1> [(intD.1
*)&<retval>]+4 S4 A32])
        (subreg:SI (lshiftrt:DI (subreg:DI (reg:V8SI 139 [ vect__2.14_29 ])=
 0)
                (const_int 32 [0x20])) 0)) "/app/example.cpp":36:12 276
{*movsi_internal}
     (expr_list:REG_DEAD (reg:DI 149)
        (nil)))

Confirmed.=