[Bug target/116280] New: [15 Regression] RISC-V: expected mode RVVMF8QI for operand 2 of insn pred_vwsllrvvmf4hi but got mode RVVMF2SI

[Bug target/116280] New: [15 Regression] RISC-V: expected mode RVVMF8QI for operand 2 of insn pred_vwsllrvvmf4hi but got mode RVVMF2SI

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116280

            Bug ID: 116280
           Summary: [15 Regression] RISC-V: expected mode RVVMF8QI for
                    operand 2 of insn pred_vwsllrvvmf4hi but got mode
                    RVVMF2SI
           Product: gcc
           Version: 15.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

Created attachment 58865
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58865&action=edit
Unreduced testcase

Testcase:
short a;
char b;
void c(int e[][1][1], char f[][1][1][1][1]) {
  for (int g; b;)
    for (;;)
      for (int h; h < 4073709551572ULL; h += 18446744073709551612U)
        a = f[2][2][1][4073709551612][1] << e[1][1][g];
}


Command/backtrace:
> /scratch/tc-testing/tc-compiler-fuzz-trunk/build-gcv/bin/riscv64-unknown-linux-gnu-gcc -O3 -march=rv64imdzvbb func.c -c -o /dev/null
during RTL pass: split1
func.c: In function 'c':
func.c:8:1: internal compiler error: expected mode RVVMF4QI for operand 2 of
insn pred_vwsllrvvmf2hi but got mode RVVM1SI.

    8 | }
      | ^
0x2de6365 internal_error(char const*, ...)
        ../../../gcc/gcc/diagnostic-global-context.cc:491
0x1878b7e riscv_vector::insn_expander<11>::emit_insn(insn_code, rtx_def**)
        ../../../gcc/gcc/config/riscv/riscv-v.cc:299
0x186fd1c riscv_vector::emit_vlmax_insn(unsigned int, unsigned int, rtx_def**)
        ../../../gcc/gcc/config/riscv/riscv-v.cc:398
0x20b9a9f gen_split_10234(rtx_insn*, rtx_def**)
        ../../../gcc/gcc/config/riscv/autovec-opt.md:1550
0xf04134 try_split(rtx_def*, rtx_insn*, int)
        ../../../gcc/gcc/emit-rtl.cc:3941
0x12df0c5 split_insn
        ../../../gcc/gcc/recog.cc:3462
0x12e4127 split_all_insns()
        ../../../gcc/gcc/recog.cc:3566
0x12e41ec execute
        ../../../gcc/gcc/recog.cc:4490
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

Godbolt: https://godbolt.org/z/WcKErGs9M

Found via fuzzer

[Bug target/116280] [15 Regression] RISC-V: expected mode RVVMF8QI for operand 2 of insn pred_vwsllrvvmf4hi but got mode RVVMF2SI

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116280

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |ice-on-valid-code
   Target Milestone|---                         |15.0

[Bug target/116280] [15 Regression] RISC-V: expected mode RVVMF8QI for operand 2 of insn pred_vwsllrvvmf4hi but got mode RVVMF2SI

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116280

--- Comment #1 from Li Pan <pan2.li at intel dot com> ---
Looks like some typos in md files, let me take a look.

[Bug target/116280] [15 Regression] RISC-V: expected mode RVVMF8QI for operand 2 of insn pred_vwsllrvvmf4hi but got mode RVVMF2SI

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116280

--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1

commit r15-2969-g06ae7bc1345a31a5f23dc86b348a1bef59bb3cc1
Author: Pan Li <pan2.li@intel.com>
Date:   Sat Aug 17 09:25:58 2024 -0600

    RISC-V: Bugfix incorrect operand for vwsll auto-vect

    This patch would like to fix one ICE when rv64gcv_zvbb for vwsll.
    Consider below example.

    void vwsll_vv_test (short *restrict dst, char *restrict a,
                        int *restrict b, int n)
    {
      for (int i = 0; i < n; i++)
        dst[i] = a[i] << b[i];
    }

    It will hit the vwsll pattern with following operands.
    operand 0 -> (reg:RVVMF2HI 146 [ vect__7.13 ])
    operand 1 -> (reg:RVVMF4QI 165 [ vect_cst__33 ])
    operand 2 -> (reg:RVVM1SI 171 [ vect_cst__36 ])

    According to the ISA, operand 2 should be the same as operand 1.
    Aka operand 2 should have RVVMF4QI mode as above.  Thus,  add
    quad truncation for operand 2 before emit vwsll.

    The below test suites are passed for this patch.
    * The rv64gcv fully regression test.

            PR target/116280

    gcc/ChangeLog:

            * config/riscv/autovec-opt.md: Add quad truncation to
            align the mode requirement for vwsll.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr116280-1.c: New test.
            * gcc.target/riscv/rvv/base/pr116280-2.c: New test.

[Bug target/116280] [15 Regression] RISC-V: expected mode RVVMF8QI for operand 2 of insn pred_vwsllrvvmf4hi but got mode RVVMF2SI

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116280

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED
                 CC|                            |law at gcc dot gnu.org

--- Comment #3 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Should be fixed on the trunk now.