[Bug c++/116389] New: ICE in extract_constrain_insn for avrtiny and -O2

[Bug c++/116389] New: ICE in extract_constrain_insn for avrtiny and -O2

[dv at vollmann dot ch]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389

            Bug ID: 116389
           Summary: ICE in extract_constrain_insn for avrtiny and -O2
           Product: gcc
           Version: 15.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c++
          Assignee: unassigned at gcc dot gnu.org
          Reporter: dv at vollmann dot ch
  Target Milestone: ---
            Target: avr

Created attachment 58938
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58938&action=edit
Preprocessed source using -freport-bug

/ssd1/build/avr/gcc-bug/avr/avrtiny/libstdc++-v3/include/bits/locale_facets_nonio.tcc:578:7:
error: insn does not satisfy its constraints:
  578 |       }
      |       ^
(insn 180 900 181 27 (set (mem/c:SI (plus:HI (reg/f:HI 28 r28)
                (const_int 28 [0x1c])) [91 %sfp+28 S4 A8])
        (reg:SI 30 r30))
"/ssd1/build/avr/gcc-bug/avr/avrtiny/libstdc++-v3/include/bits/locale_facets_nonio.tcc":477:14
119 {*movsi_split}
     (nil))
during RTL pass: postreload
/ssd1/build/avr/gcc-bug/avr/avrtiny/libstdc++-v3/include/bits/locale_facets_nonio.tcc:578:7:
internal compiler error: in extract_constrain_insn, at recog.cc:2783
0x1cf6290 internal_error(char const*, ...)
        /ssd1/build/src/gcc/gcc/diagnostic-global-context.cc:491
0x6ea6b7 fancy_abort(char const*, int, char const*)
        /ssd1/build/src/gcc/gcc/diagnostic.cc:1772
0x59b339 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /ssd1/build/src/gcc/gcc/rtl-error.cc:108
0x59b35f _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        /ssd1/build/src/gcc/gcc/rtl-error.cc:118
0x599e91 extract_constrain_insn(rtx_insn*)
        /ssd1/build/src/gcc/gcc/recog.cc:2783
0xeeb2d6 reload_cse_simplify_operands
        /ssd1/build/src/gcc/gcc/postreload.cc:396
0xeebe65 reload_cse_simplify
        /ssd1/build/src/gcc/gcc/postreload.cc:179
0xeebe65 reload_cse_regs_1
        /ssd1/build/src/gcc/gcc/postreload.cc:227
0xeedf9b reload_cse_regs
        /ssd1/build/src/gcc/gcc/postreload.cc:65
0xeedf9b execute
        /ssd1/build/src/gcc/gcc/postreload.cc:2366

This happens when trying to build libstdc++, the file is
libstdc++-v3/src/c++11/locale-inst.cc.
It only occurs for avrtiny and -O2, not for other AVR archs or other
optimization levels (Os, O1, O3 and O4 build fine).

[Bug rtl-optimization/116389] [avr][15 regression] ICE in extract_constrain_insn for avrtiny and -O2

[gjl at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389

Georg-Johann Lay <gjl at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW
                 CC|                            |law at gcc dot gnu.org
   Last reconfirmed|                            |2024-08-17
            Summary|ICE in                      |[avr][15 regression] ICE in
                   |extract_constrain_insn for  |extract_constrain_insn for
                   |avrtiny and -O2             |avrtiny and -O2
           Keywords|                            |ra
             Blocks|                            |56183
          Component|target                      |rtl-optimization

--- Comment #1 from Georg-Johann Lay <gjl at gcc dot gnu.org> ---
There is this insn from ext-dce (from -fdump-rtl-ira-details):

(insn 180 179 181 26 (set (reg/v:SI 70 [ __paddec ])
        (subreg:SI (reg/v:HI 78 [ __len ]) 0))
"/ssd1/build/avr/gcc-bug/avr/avrtiny/libstdc++-v3/include/bits/locale_facets_nonio.tcc":477:14
119 {*movsi_split}
     (nil))

Register allocation then assigns R30:HI to pseudo 78, but due to the
paradoxical subreg, this becomes R30:SI which is not a valid hard register
because R31 is the last valid general-purpose register.  The reload dump (from
-fdump-rtl-reload-details):

(insn 180 900 181 27 (set (mem/c:SI (plus:HI (reg/f:HI 28 r28)
                (const_int 28 [0x1c])) [91 %sfp+28 S4 A8])
        (reg:SI 30 r30))
"/ssd1/build/avr/gcc-bug/avr/avrtiny/libstdc++-v3/inclu

This insn is not valid because R30:SI is not a valid hard reg, so it's no
wonder no valid insn constraint alternative is found and hence ICE.

So the question is whether that paradoxical subreg from ext-dce is valid in the
first place? Or is it a register allocation issue?

As an aside, -mlra also ICEs because the code is too complicated for LRA
(doesn't find reloads.


Referenced Bugs:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56183
[Bug 56183] [meta-bug][avr] Problems with register allocation

[Bug rtl-optimization/116389] [avr][15 regression] ICE in extract_constrain_insn for avrtiny and -O2

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389

--- Comment #2 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Yes, a paradoxical is precisely what we expect and want here.  This sounds like
either a reload bug (definitely possible, I'm still chasing one of these over
on the m68k) or a backend bug with avr.

[Bug rtl-optimization/116389] [avr][15 regression] ICE in extract_constrain_insn for avrtiny and -O2

[gjl at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389

--- Comment #3 from Georg-Johann Lay <gjl at gcc dot gnu.org> ---
(In reply to Jeffrey A. Law from comment #2)
> or a backend bug with avr.

I don't see what the avr backend is doing wrong.  I played around with
avr_hard_regno_mode_ok etc. and denied SImode for R30, but to no avail.

R30 is already assigned by IRA, and it appears that IRA doesn't understand the
impact of a paradoxical subreg; pseudo 78 should be treated as if it had
SImode, instead of the actual mode of that pseudo.

[Bug rtl-optimization/116389] [avr][15 regression] ICE in extract_constrain_insn for avrtiny and -O2

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389

--- Comment #4 from Jeffrey A. Law <law at gcc dot gnu.org> ---
I'm pretty confident IRA knows the basics of paradoxicals.  The concept of
paradoxicals has been around since the gcc-1 era and Vlad is well aware of how
paradoxicals work.

So while there may be a bug, I doubt it's baked in so deep that "IRA doesn't
understand the impact of paradoxical subreg" is a reasonable assessment.

If IRA is allocating r30 for SImode, and that's not valid on your target,
you'll need to debug why.

[Bug rtl-optimization/116389] [avr][15 regression] ICE in extract_constrain_insn for avrtiny and -O2

[gjl at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389

--- Comment #5 from Georg-Johann Lay <gjl at gcc dot gnu.org> ---
(In reply to Jeffrey A. Law from comment #4)
> "IRA doesn't understand the impact of paradoxical subreg" is a
> reasonable assessment.
RA should either assess the validity of a paradoxical subreg in the mode of a
subreg (SImode in this case), or just deal with the payload mode (HImode in
this case).

Paradoxicals behave differently on machines with small word size (like avr / 8
bits) than on a 32-bit machine:

On avr, HARD_REGNO_NREGS is larger for SImode (4 regs) than for HImode (2
regs).

Whereas on a 32-bit machine, QImode, HImode, SImode all just occupy one hard
reg.

Anyway, RA should just use the SUBREG_REG's mode, no?  What's the point of
letting ext-dce mark parts of a register as unused, when these parts are still
moved around and consume space on the stack and in the register file?

[Bug rtl-optimization/116389] [avr][15 regression] ICE in extract_constrain_insn for avrtiny and -O2

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389

--- Comment #6 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Sorry should have written "is _not_ a reasonable assessment" in my prior
message.

RA does assess validity and there's nothing special about avr here and
paradoxicals, unless the backend is doing something incorrect.

You really need to debug why IRA is making an invalid assignment.

[Bug rtl-optimization/116389] [15 regression] [avr] ICE in extract_constrain_insn for avrtiny and -O2 with ext-dce

[gjl at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389

--- Comment #7 from Georg-Johann Lay <gjl at gcc dot gnu.org> ---
Created attachment 58955
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58955&action=edit
Reduced C test case

$ avr-gcc pr116389-red.c -S -Os -mmcu=avrtiny

struct T { int val; };

void f_int (int);
char* get_pos (void);
struct T* get_pT (void);

void func (char i)
{
    struct T t = * get_pT ();
    unsigned diff = get_pos () - &i;

    if (diff)
    {
        long val32 = t.val;
        if (get_pos ())
            val32 = diff;
        if (get_pos ())
            f_int (2 * val32);
    }
}

[Bug rtl-optimization/116389] [15 regression] [avr] ICE in extract_constrain_insn for avrtiny and -O2 with ext-dce

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |15.0

[Bug rtl-optimization/116389] [15 regression] [avr] ICE in extract_constrain_insn for avrtiny and -O2 with ext-dce

[gjl at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116389

--- Comment #8 from Georg-Johann Lay <gjl at gcc dot gnu.org> ---
As it appears, this ICE only occurs with reload (-mno-lra) but not with LRA
(-mlra).  Provided PR116326 is fixed.