[Bug target/116467] New: missed optimization: zero-extension duplicated on xtensa

[Bug target/116467] New: missed optimization: zero-extension duplicated on xtensa

[rsaxvc at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116467

            Bug ID: 116467
           Summary: missed optimization: zero-extension duplicated on
                    xtensa
           Product: gcc
           Version: 12.2.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: rsaxvc at gmail dot com
  Target Milestone: ---

On GCC 12.2.0, -O2 -Wall -Wextra, the following code:

    #include <stdint.h>

    __attribute__ ((noinline)) uint32_t callee(uint32_t x, uint16_t y){
        return x + y;
    }

    __attribute__ ((noinline)) uint32_t caller(uint32_t x, uint32_t y){
        return callee(x, y);
    }

compiles to these xtensa instructions:

    callee:
            entry   sp, 32
            extui   a3, a3, 0, 16
            add.n   a2, a3, a2
            retw.n
    caller:
            entry   sp, 32
            extui   a11, a3, 0, 16
            mov.n   a10, a2
            call8   callee
            mov.n   a2, a10
            retw.n

I was surprised to find that zero-extension (extui rDest, rSource, 0, 16)
occurs twice, once in each function. On other targets like ARM32, it looks like
uint16_t passed in a register is assumed to be passed zero-extended, so the
callee does not need to repeat it. ARM32, GCC12.2, same flags:

    callee:
            add     r0, r0, r1
            bx      lr
    caller:
            uxth    r1, r1 //similar to extui, .., .., 0, 16
            b       callee

Could xtensa do the same?

[Bug target/116467] missed optimization: zero-extension duplicated on xtensa

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116467

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|                            |xtensa
           Keywords|                            |missed-optimization

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
It probably can, but it depends on the guarantees set by the ABI if there is
any such written.

[Bug target/116467] missed optimization: zero-extension duplicated on xtensa

[rsaxvc at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116467

--- Comment #2 from rsaxvc at gmail dot com ---
I had wondered about that too but hadn't been able to find anything about it.
User ccrause on esp32.com knew where it was though. From
https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/silicon-solutions/compute-ip/isa-summary.pdf.

From section 10.1.4, Argument Passing in AR Registers

> All arguments consist of an integral number of 4-byte words. Thus, the minimum argument size is one word. Integer values smaller than a word (that is, char and short) are stored in the least significant portion of the argument word, with the upper bits set to zero for unsigned values or sign-extended for signed values.

From section 10.1.5, Return Values in AR Registers:

> Return values smaller than a word are stored in the least-significant part of AR[2], with the upper bits set to zero for unsigned values or sign-extended for signed values.

So I think extending just once should be safe, at least for LX cores.