From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 6AFB8384C001; Tue, 26 Jan 2021 13:43:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6AFB8384C001 From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/21182] [8/9/10/11 Regression] gcc can use registers but uses stack instead Date: Tue, 26 Jan 2021 13:43:53 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 3.4.3 X-Bugzilla-Keywords: missed-optimization, ra X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 11.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jan 2021 13:43:53 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D21182 --- Comment #31 from Richard Biener --- -fno-tree-ter improves things quite a bit. With -DNAILED_REGS gimple doesn= 't do much because we treat registers as memory here. For trunk -O2 has 52 spills -O2 -fno-tree-ter has 35 spills -O2 -fno-tree-ter -fschedule-insns has 74 spills -O2 -fno-tree-ter -fschedule-insns -fsched-pressure has 18 spills -O2 -fschedule-insns -fsched-pressure has 17 spills to me this really hints at out-of-SSA producing a very bad initial schedule, by TER but also likely due to folding & friends doing random stmt placing (it's all a single BB). I think we'd benefit quite a bit with killing TER (doing all interesting bits pre-RTL or via SSA RTL forwprop) and ordering SSA def expansion for optimal register pressure.=