* [Bug middle-end/35363] Missing bit field coalscing optimization
2008-02-25 5:39 [Bug middle-end/35363] New: Missing bit field coalscing optimization xinliangli at gmail dot com
@ 2008-02-25 11:37 ` rguenth at gcc dot gnu dot org
2008-02-25 18:39 ` [Bug target/35363] " pinskia at gcc dot gnu dot org
` (4 subsequent siblings)
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From: rguenth at gcc dot gnu dot org @ 2008-02-25 11:37 UTC (permalink / raw)
To: gcc-bugs
------- Comment #1 from rguenth at gcc dot gnu dot org 2008-02-25 11:36 -------
(please make our work easier and make the initial reports Severity enhancement
and add missed-optimization as a Keyword and make the report against a
gcc version, preferably 4.3.0 or 4.4.0; testcases ready for inclusion into
the gcc testsuite would be nice as well, as well as checking for duplicate
reports yourself).
This testcase actually requires one load, one and (mask out bits in the
affected bitfield parts), one or and one store. The MEM_REF work
might lay grounds for this to work, it makes the read-modify-write
cycles explicit on the tree level and thus allows the loads and
stores to be CSEd.
--
rguenth at gcc dot gnu dot org changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |rguenth at gcc dot gnu dot
| |org
Severity|normal |enhancement
Status|UNCONFIRMED |NEW
Ever Confirmed|0 |1
Keywords| |missed-optimization
Last reconfirmed|0000-00-00 00:00:00 |2008-02-25 11:36:39
date| |
Version|unknown |4.3.0
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363
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* [Bug target/35363] Missing bit field coalscing optimization
2008-02-25 5:39 [Bug middle-end/35363] New: Missing bit field coalscing optimization xinliangli at gmail dot com
2008-02-25 11:37 ` [Bug middle-end/35363] " rguenth at gcc dot gnu dot org
@ 2008-02-25 18:39 ` pinskia at gcc dot gnu dot org
2008-02-25 18:45 ` [Bug target/35363] Missing bit field coalescing optimization rguenth at gcc dot gnu dot org
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: pinskia at gcc dot gnu dot org @ 2008-02-25 18:39 UTC (permalink / raw)
To: gcc-bugs
------- Comment #2 from pinskia at gcc dot gnu dot org 2008-02-25 18:38 -------
This works correctly for PowerPC*.
PPC64 (with GCC 4.0.1):
lwz r0,0(r11)
rlwinm r0,r0,0,3,31
oris r0,r0,0x4000
and r0,r0,r9
oris r0,r0,0xc00
and r0,r0,r2
ori r0,r0,1024
stw r0,0(r11)
PPC32 (GCC 4.0.2):
lwz r0,0(r9)
rlwimi r0,r2,29,0,2
li r2,3
rlwimi r0,r2,26,3,5
li r2,8
rlwimi r0,r2,7,8,24
stw r0,0(r9)
--
pinskia at gcc dot gnu dot org changed:
What |Removed |Added
----------------------------------------------------------------------------
Component|middle-end |target
GCC target triplet| |x86_64-*-*
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363
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* [Bug target/35363] Missing bit field coalescing optimization
2008-02-25 5:39 [Bug middle-end/35363] New: Missing bit field coalscing optimization xinliangli at gmail dot com
2008-02-25 11:37 ` [Bug middle-end/35363] " rguenth at gcc dot gnu dot org
2008-02-25 18:39 ` [Bug target/35363] " pinskia at gcc dot gnu dot org
@ 2008-02-25 18:45 ` rguenth at gcc dot gnu dot org
2008-02-25 18:50 ` rguenth at gcc dot gnu dot org
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: rguenth at gcc dot gnu dot org @ 2008-02-25 18:45 UTC (permalink / raw)
To: gcc-bugs
------- Comment #3 from rguenth at gcc dot gnu dot org 2008-02-25 18:44 -------
I would expect the equivalent of
int tmp = a;
tmp &= 0x0030; // fix the mask to be correct, all bits of b3
tmp |= 2 | 3 | 8; // constant folded and properly shifted
a = tmp;
I still see three ORs for ppc64 and non-combined rlwimi ops for ppc32.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363
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* [Bug target/35363] Missing bit field coalescing optimization
2008-02-25 5:39 [Bug middle-end/35363] New: Missing bit field coalscing optimization xinliangli at gmail dot com
` (2 preceding siblings ...)
2008-02-25 18:45 ` [Bug target/35363] Missing bit field coalescing optimization rguenth at gcc dot gnu dot org
@ 2008-02-25 18:50 ` rguenth at gcc dot gnu dot org
2008-02-25 18:52 ` rguenth at gcc dot gnu dot org
2008-02-25 18:54 ` rguenth at gcc dot gnu dot org
5 siblings, 0 replies; 7+ messages in thread
From: rguenth at gcc dot gnu dot org @ 2008-02-25 18:50 UTC (permalink / raw)
To: gcc-bugs
------- Comment #4 from rguenth at gcc dot gnu dot org 2008-02-25 18:49 -------
So, the same code should be generated for
union {
struct {
int b1: 3;
int b2: 3;
int b3: 2;
int b4: 17;
}a;
int b;
} a;
void foo()
{
a.a.b1 = 2;
a.a.b2 = 3;
a.a.b4 = 8;
}
void bar()
{
a.b = (a.b & (-1u >> (sizeof(a.b)*8 - 2) << 6)) | 2 | (3 << 3) | (8 << 17);
}
modulo errors I made in the bar() case ;)
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363
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* [Bug target/35363] Missing bit field coalescing optimization
2008-02-25 5:39 [Bug middle-end/35363] New: Missing bit field coalscing optimization xinliangli at gmail dot com
` (3 preceding siblings ...)
2008-02-25 18:50 ` rguenth at gcc dot gnu dot org
@ 2008-02-25 18:52 ` rguenth at gcc dot gnu dot org
2008-02-25 18:54 ` rguenth at gcc dot gnu dot org
5 siblings, 0 replies; 7+ messages in thread
From: rguenth at gcc dot gnu dot org @ 2008-02-25 18:52 UTC (permalink / raw)
To: gcc-bugs
------- Comment #5 from rguenth at gcc dot gnu dot org 2008-02-25 18:51 -------
With MEM_REF I get on i686
foo:
movl a, %eax
pushl %ebp
movl %esp, %ebp
popl %ebp
andl $-33554240, %eax
orl $2074, %eax
movl %eax, a
ret
.size foo, .-foo
.p2align 4,,15
.globl bar
.type bar, @function
bar:
movl a, %eax
pushl %ebp
movl %esp, %ebp
popl %ebp
andl $192, %eax
orl $1048602, %eax
movl %eax, a
ret
which shows that I made an error in the source ;)
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363
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* [Bug target/35363] Missing bit field coalescing optimization
2008-02-25 5:39 [Bug middle-end/35363] New: Missing bit field coalscing optimization xinliangli at gmail dot com
` (4 preceding siblings ...)
2008-02-25 18:52 ` rguenth at gcc dot gnu dot org
@ 2008-02-25 18:54 ` rguenth at gcc dot gnu dot org
5 siblings, 0 replies; 7+ messages in thread
From: rguenth at gcc dot gnu dot org @ 2008-02-25 18:54 UTC (permalink / raw)
To: gcc-bugs
------- Comment #6 from rguenth at gcc dot gnu dot org 2008-02-25 18:54 -------
The IL after MEM_REF lowering looks like
bar ()
{
int D.1193;
unsigned int D.1192;
unsigned int D.1191;
unsigned int D.1190;
int D.1189;
D.1189 = MEM <int {0}, &a>;
D.1190 = (unsigned int) D.1189;
D.1191 = D.1190 & 192;
D.1192 = D.1191 | 1048602;
D.1193 = (int) D.1192;
MEM <int {0}, &a> = D.1193;
return;
}
foo ()
{
int MEML.2;
int MEML.1;
int MEML.0;
MEML.0 = MEM <int {0}, &a>;
MEML.0 = BIT_FIELD_EXPR <MEML.0, 2, 3, 0>;
MEM <int {0}, &a> = MEML.0;
MEML.1 = MEM <int {0}, &a>;
MEML.1 = BIT_FIELD_EXPR <MEML.1, 3, 3, 3>;
MEM <int {0}, &a> = MEML.1;
MEML.2 = MEM <int {0}, &a>;
MEML.2 = BIT_FIELD_EXPR <MEML.2, 8, 17, 8>;
MEM <int {0}, &a> = MEML.2;
return;
}
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363
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