From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20037 invoked by alias); 27 Sep 2009 09:13:20 -0000 Received: (qmail 19999 invoked by uid 48); 27 Sep 2009 09:13:07 -0000 Date: Sun, 27 Sep 2009 09:13:00 -0000 Subject: [Bug target/41481] New: missed optimization in cse X-Bugzilla-Reason: CC Message-ID: Reply-To: gcc-bugzilla@gcc.gnu.org To: gcc-bugs@gcc.gnu.org From: "carrot at google dot com" Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2009-09/txt/msg02465.txt.bz2 Compile following code with options -Os -march=armv5te -mthumb, class A { public: int ah; unsigned field : 2; }; void foo(A* p) { p->ah = 1; p->field = 1; } We can get: mov r3, #1 // A str r3, [r0] ldrb r3, [r0, #4] mov r2, #3 bic r3, r3, r2 mov r2, #1 // B orr r3, r3, r2 strb r3, [r0, #4] @ sp needed for prologue bx lr Both instruction A and B load a constant 1 into register. We can load 1 into r1 in instruction A and use r1 when constant 1 is required. So instruction B can be removed. cse pass doesn't find this opportunity is because it needs all expressions to be of the same mode. But in rtl level the first 1 is in mode SI and the second 1 is in mode QI. Arm doesn't has any physical register of QI mode, so all of them are put into 32 bit physical register and causes redundant load of constant 1. -- Summary: missed optimization in cse Product: gcc Version: 4.5.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target AssignedTo: unassigned at gcc dot gnu dot org ReportedBy: carrot at google dot com GCC build triplet: i686-linux GCC host triplet: i686-linux GCC target triplet: arm-eabi http://gcc.gnu.org/bugzilla/show_bug.cgi?id=41481