[Bug middle-end/42972] Very bad bit field code

[Bug middle-end/42972] Very bad bit field code

[steven at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42972

Steven Bosscher <steven at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|arm-elf                     |arm-eabi
   Last reconfirmed|2010-02-05 12:45:53         |2012-03-18 12:45:53

--- Comment #6 from Steven Bosscher <steven at gcc dot gnu.org> 2012-03-18 23:07:45 UTC ---
Trunk r185508 produces the same code as quoted in comment #0.

[Bug middle-end/42972] Very bad bit field code

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42972

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Severity|normal                      |enhancement
                 CC|                            |pinskia at gcc dot gnu.org

[Bug middle-end/42972] Very bad bit field code

[matz at gcc dot gnu dot org]

------- Comment #5 from matz at gcc dot gnu dot org  2010-02-05 15:36 -------
The code for the if() looks sane on x86-64:
-----------------------------------------
;; if (D.2729_8 != 0)

(insn 16 15 17 pr42972.c:10 (set (reg:QI 87)
        (mem/s:QI (reg/f:DI 82 [ D.2727 ]) [0 S1 A32])) -1 (nil))

(insn 17 16 18 pr42972.c:10 (parallel [
            (set (reg:QI 86)
                (and:QI (reg:QI 87)
                    (const_int 1 [0x1])))
            (clobber (reg:CC 17 flags))
        ]) -1 (expr_list:REG_EQUAL (and:QI (mem/s:QI (reg/f:DI 82 [ D.2727 ])
                                            [0 S1 A32])
            (const_int 1 [0x1]))
        (nil)))

(insn 18 17 19 pr42972.c:10 (set (reg:CCZ 17 flags)
        (compare:CCZ (reg:QI 86)
            (const_int 0 [0x0]))) -1 (nil))

(jump_insn 19 18 0 pr42972.c:10 (set (pc)
        (if_then_else (eq (reg:CCZ 17 flags)
                (const_int 0 [0x0]))
            (label_ref 0)
            (pc))) -1 (expr_list:REG_BR_PROB (const_int 5000 [0x1388])
        (nil)))
---------------------------------

Btw, instructions marked for forwarding (by TER) are not expanded to useless
code, but not expanded at all (or better said, only at the point of use).

The back-and-forth between QImode and SImode on arm seems to stem from
register promotion trying really hard to work on only SImode regs.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42972

[Bug middle-end/42972] Very bad bit field code

[rguenth at gcc dot gnu dot org]

------- Comment #4 from rguenth at gcc dot gnu dot org  2010-02-05 13:25 -------
(In reply to comment #1)
> In the .expand dump there is already something funny about the code generated
> for the bit field expressions.
> 
> For example the code generated for this:
>   D.1966_8 = D.1965_7 & 1;
>   if (D.1966_8 != 0)
> 
> TER will perform the forward substitution:
> D.1966_8 replace with --> D.1966_8 = D.1965_7 & 1;

Note that this dump is misleading.  The expression is only _marked_ for
possible forwarding.  It is the resposibility of the individual expanders
to do the expression lookup and in-place expansion.
And of course forwarded statements are still regularly expanded anyway
(well, to dead code) - that's probably what you see.


-- 

rguenth at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |matz at gcc dot gnu dot org


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42972

[Bug middle-end/42972] Very bad bit field code

[rguenth at gcc dot gnu dot org]

------- Comment #3 from rguenth at gcc dot gnu dot org  2010-02-05 13:17 -------
On the (retired) mem-ref branch bitfield loads/stores were lowered very early
to read-extract-modify-write operations so the tree level would have optimized
this.

But of course people complained that architectures that can do bitfield
stores would be pessimized if we do not retain the funny BIT_FIELD_REFs
of memory.

Basically without some form of lowering the tree level is lost.

mem-ref branch lowered the fn to

  i = 0;
  <D.1562>:;
  D.1564 = (long unsigned int) i;
  D.1565 = D.1564 * 4;
  D.1566 = p + D.1565;
  MEML.0 = IMEM <unsigned int {2}, D.1566>;
  D.1567 = BIT_FIELD_REF <MEML.0, 1, 0>;
  if (D.1567 != 0) goto <D.1574>; else goto <D.1575>;
  <D.1574>:;
  D.1564 = (long unsigned int) i;
  D.1565 = D.1564 * 4;
  D.1566 = p + D.1565;
  D.1564 = (long unsigned int) i;
  D.1565 = D.1564 * 4;
  D.1566 = p + D.1565;
  MEML.1 = IMEM <unsigned int {2}, D.1566>;
  D.1568 = BIT_FIELD_REF <MEML.1, 31, 1>;
  D.1569 = (int) D.1568;
  D.1570 = D.1569 + a;
  D.1571 = (unsigned int) D.1570;
  D.1572 = (<unnamed-unsigned:31>) D.1571;
  MEML.2 = IMEM <unsigned int {2}, D.1566>;
  MEML.2 = BIT_FIELD_EXPR <MEML.2, D.1572, 31, 1>;
  IMEM <unsigned int {2}, D.1566> = MEML.2;
  <D.1575>:;
  i = i + 1;
  if (i < n) goto <D.1562>; else goto <D.1563>;
  <D.1563>:;
  return;

so FRE sees the redundant load and we expand from

<bb 2>:
  ivtmp.20_15 = (unsigned int *) p_5(D);

<bb 3>:
  # ivtmp.20_13 = PHI <ivtmp.20_15(2), ivtmp.20_22(5)>
  # i_1 = PHI <0(2), i_24(5)>
  MEML.0_7 = IMEM <unsigned int {2}, ivtmp.20_13>;
  D.1567_8 = BIT_FIELD_REF <MEML.0_7, 1, 0>;
  if (D.1567_8 != 0)
    goto <bb 4>;
  else
    goto <bb 5>;

<bb 4>:
  D.1568_16 = BIT_FIELD_REF <MEML.0_7, 31, 1>;
  D.1569_17 = (int) D.1568_16;
  D.1570_19 = D.1569_17 + a_18(D);
  D.1571_20 = (unsigned int) D.1570_19;
  D.1572_21 = (<unnamed-unsigned:31>) D.1571_20;
  MEML.2_23 = BIT_FIELD_EXPR <MEML.0_7, D.1572_21, 31, 1>;
  IMEM <unsigned int {2}, ivtmp.20_13> = MEML.2_23;

<bb 5>:
  i_24 = i_1 + 1;
  ivtmp.20_22 = ivtmp.20_13 + 4;
  if (i_24 < n_25(D))
    goto <bb 3>;
  else
    goto <bb 6>;

<bb 6>:
  return;


on x86_64 the generated code was

func:
.LFB2:
        movl    %edx, %r8d
        xorl    %ecx, %ecx
        .p2align 4,,10
        .p2align 3
.L3:
        movl    (%rdi), %eax
        testb   $1, %al
        je      .L2
        movl    %eax, %edx
        shrl    %eax
        addl    %r8d, %eax
        andl    $1, %edx
        addl    %eax, %eax
        orl     %eax, %edx
        movl    %edx, (%rdi)
.L2:
        addl    $1, %ecx
        addq    $4, %rdi
        cmpl    %esi, %ecx
        jl      .L3
        rep
        ret


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42972

[Bug middle-end/42972] Very bad bit field code

[steven at gcc dot gnu dot org]

------- Comment #2 from steven at gcc dot gnu dot org  2010-02-05 12:45 -------
This is both a tree-optimization and an rtl-optimization problem, so setting
component to "middle-end" (there is no generic "optimization" component
anymore).


-- 

steven at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
          Component|tree-optimization           |middle-end
     Ever Confirmed|0                           |1
   Last reconfirmed|0000-00-00 00:00:00         |2010-02-05 12:45:53
               date|                            |


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42972