[Bug target/46098] New: [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[Bug target/46098] New: [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[zsojka at seznam dot cz]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

           Summary: [4.5/4.6 Regression] ICE: in extract_insn, at
                    recog.c:2100 with -msse3 -ffloat-store and
                    __builtin_ia32_loadupd()
           Product: gcc
           Version: 4.6.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: zsojka@seznam.cz


----- testcase.c -----
typedef double v2df __attribute__((vector_size (16)));

v2df foo (double *d)
{
  return __builtin_ia32_loadupd (d);
}
----------------------

Compiler output:
$ gcc -msse3 -ffloat-store testcase.c
testcase.c: In function 'foo':
testcase.c:6:1: error: unrecognizable insn:
(insn 7 6 8 3 (set (mem/c/i:V2DF (plus:DI (reg/f:DI 54 virtual-stack-vars)
                (const_int -16 [0xfffffffffffffff0])) [0 D.2706+0 S16 A128])
        (unspec:V2DF [
                (mem:V2DF (reg:DI 60) [0 S16 A8])
            ] UNSPEC_MOVU)) testcase.c:5 -1
     (nil))
testcase.c:6:1: internal compiler error: in extract_insn, at recog.c:2110
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://gcc.gnu.org/bugs.html> for instructions.

Tested revisions:
r165719 - crash
r153685 - crash
4.5 r163761 - crash
4.4 r160770 - OK

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[hjl.tools at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

H.J. Lu <hjl.tools at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2010.10.20 16:58:52
                 CC|                            |hjl.tools at gmail dot com,
                   |                            |matz at gcc dot gnu.org
   Target Milestone|---                         |4.6.0
     Ever Confirmed|0                           |1

--- Comment #1 from H.J. Lu <hjl.tools at gmail dot com> 2010-10-20 16:58:52 UTC ---
It is caused by revision 146817:

http://gcc.gnu.org/ml/gcc-cvs/2009-04/msg01459.html

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[matz at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

Michael Matz <matz at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |hubicka at gcc dot gnu.org,
                   |                            |uros at gcc dot gnu.org

--- Comment #2 from Michael Matz <matz at gcc dot gnu.org> 2010-10-21 14:33:15 UTC ---
Well, that's a problem of the target.  The pattern that is supposed to match
is:

(define_insn "<sse>_movu<ssemodesuffix>"
  [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m")
        (unspec:SSEMODEF2P
          [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")]
          UNSPEC_MOVU))]
  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  ...

So, the predicates are nonimmediate_operand for both.  The additional
matching condition is that not both arguments are memory.  They are here,
hence nothing matches.  But if this is the only pattern that could match
the RTL code then the builtin expander has the obligation to create patterns
that are matchable.  But that's not what ix86_expand_special_args_builtin is
doing here.

In particular it detects that nargs=1, klass=load, memory=0.  That means the
first (and only) argument has to be memory.  Nothing is said about the target.
The routine then proceeds to not change the target, because:

  if (klass == store)
    ...
  else
    {
      arg_adjust = 0;
      if (optimize
          || target == 0
          || GET_MODE (target) != tmode
          || !insn_p->operand[0].predicate (target, tmode))
        target = gen_reg_rtx (tmode);
    }

target is
  (mem/c/i:V2DF (plus:DI (reg/f:DI 54 virtual-stack-vars)
        (const_int -16 [0xfffffffffffffff0])) [0 D.2706+0 S16 A128])
The target _does_ match the predicate, hence no change occurs.
Furthermore in the loop over arguments:

  for (i = 0; i < nargs; i++)
    {
      if (last_arg_constant && (i + 1) == nargs)
        ...
      else
        {
          if (i == memory)
            {
              /* This must be the memory operand.  */
              op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
              gcc_assert (GET_MODE (op) == mode
                          || GET_MODE (op) == VOIDmode);
            }
          ...
        }

Here we would explicitely construct a memory argument, even if it isn't
already, irrespective if the predicate matches or not.  Hence, no
matter what this does it will end up with a pattern where target and
argument are both MEM.  This is never matchable --> boom.

I don't know enough about the intention of the ix86_builtin expanders
to suggest where to fix this.  One alternative seems to be to adjust
the pattern to only accept register_operand in the destination (which also
means removing one alternative and the matching condition).

Another alternative would be only removing the !(MEM && MEM) part of the
matching condition, because reload will fix up the non-matching constraints.

The third alternative would be to fix ix86_expand_special_args_builtin to
emit the correct patterns from the start.

Whatever is done, it probably also needs to be done for some other patterns.

FWIW the second alternative would look like so:
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md  (revision 165503)
+++ config/i386/sse.md  (working copy)
@@ -412,8 +412,7 @@ (define_insn "<sse>_movu<ssemodesuffix>"
        (unspec:SSEMODEF2P
          [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")]
          UNSPEC_MOVU))]
-  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
-   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
   "movu<ssemodesuffix>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
    (set_attr "movu" "1")

and fixes the bug.

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

Uros Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED

--- Comment #3 from Uros Bizjak <ubizjak at gmail dot com> 2010-10-22 09:03:01 UTC ---
(In reply to comment #2)
> Well, that's a problem of the target.  The pattern that is supposed to match
> is:
> 
> (define_insn "<sse>_movu<ssemodesuffix>"
>   [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m")
>         (unspec:SSEMODEF2P
>           [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")]
>           UNSPEC_MOVU))]
>   "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
>    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
>   ...

> The third alternative would be to fix ix86_expand_special_args_builtin to
> emit the correct patterns from the start.
> 
> Whatever is done, it probably also needs to be done for some other patterns.
> 
> FWIW the second alternative would look like so:
> Index: config/i386/sse.md
> ===================================================================
> --- config/i386/sse.md  (revision 165503)
> +++ config/i386/sse.md  (working copy)
> @@ -412,8 +412,7 @@ (define_insn "<sse>_movu<ssemodesuffix>"
>         (unspec:SSEMODEF2P
>           [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")]
>           UNSPEC_MOVU))]
> -  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
> -   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
> +  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
>    "movu<ssemodesuffix>\t{%1, %0|%0, %1}"
>    [(set_attr "type" "ssemov")
>     (set_attr "movu" "1")
> 
> and fixes the bug.

Er, no. This is a move, and all moves have the constraint that you removed.
Probably, we have to handle this via an expander that calls ix86_expand_move,
and this will fix the operands at expansion time.

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

Uros Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         AssignedTo|unassigned at gcc dot       |ubizjak at gmail dot com
                   |gnu.org                     |

--- Comment #4 from Uros Bizjak <ubizjak at gmail dot com> 2010-10-22 09:05:54 UTC ---
Hm ...

ASSIGNED to "Not yet assigned to anyone"?

"Assigned To:" field should IMO assign the bug automatically to the (logged in)
person setting the bug in ASSIGNED state.

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

--- Comment #5 from Uros Bizjak <ubizjak at gmail dot com> 2010-10-22 10:16:27 UTC ---
Created attachment 22115
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=22115
Patch in testing.

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[uros at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

--- Comment #6 from uros at gcc dot gnu.org 2010-10-22 16:13:04 UTC ---
Author: uros
Date: Fri Oct 22 16:12:57 2010
New Revision: 165845

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=165845
Log:
    PR target/46098
    * config/i386/sse.md (*avx_movu<ssemodesuffix><avxmodesuffix>):
    Rename from avx_movu<ssemodesuffix><avxmodesuffix>.
    (avx_movu<ssemodesuffix><avxmodesuffix>): New expander.
    (*<sse>_movu<ssemodesuffix>): Rename from <sse>_movu<ssemodesuffix>.
    (<sse>_movu<ssemodesuffix>): New expander.
    (*avx_movdqu<avxmodesuffix>): Rename from avx_movdqu<avxmodesuffix>.
    (avx_movdqu<avxmodesuffix>): New expander.
    (*sse2_movdqu): Rename from sse2_movdqu.
    (sse2_movdqu): New expander.

testsuite/ChangeLog:

    PR target/46098
    * gcc.target/i386/pr46098.c: New test.


Added:
    trunk/gcc/testsuite/gcc.target/i386/pr46098.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/sse.md
    trunk/gcc/testsuite/ChangeLog

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[uros at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

--- Comment #7 from uros at gcc dot gnu.org 2010-10-22 16:18:53 UTC ---
Author: uros
Date: Fri Oct 22 16:18:41 2010
New Revision: 165846

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=165846
Log:
    PR target/46098
    * config/i386/sse.md (*avx_movup<avxmodesuffixf2c><avxmodesuffix>):
    Rename from avx_movup<avxmodesuffixf2c><avxmodesuffix>.
    (avx_movup<avxmodesuffixf2c><avxmodesuffix>): New expander.
    (*<sse>_movup<ssemodesuffixf2c>): Rename from
    <sse>_movup<ssemodesuffixf2c>.
    (<sse>_movup<ssemodesuffixf2c>): New expander.
    (*avx_movdqu<avxmodesuffix>): Rename from avx_movdqu<avxmodesuffix>.
    (avx_movdqu<avxmodesuffix>): New expander.
    (*sse2_movdqu): Rename from sse2_movdqu.
    (sse2_movdqu): New expander.

testsuite/ChangeLog:

    PR target/46098
    * gcc.target/i386/pr46098.c: New test.


Added:
    branches/gcc-4_5-branch/gcc/testsuite/gcc.target/i386/pr46098.c
Modified:
    branches/gcc-4_5-branch/gcc/ChangeLog
    branches/gcc-4_5-branch/gcc/config/i386/sse.md
    branches/gcc-4_5-branch/gcc/testsuite/ChangeLog

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

Uros Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|                            |FIXED
   Target Milestone|4.6.0                       |4.5.2

--- Comment #8 from Uros Bizjak <ubizjak at gmail dot com> 2010-10-22 16:23:24 UTC ---
Fixed.

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

Uros Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|RESOLVED                    |ASSIGNED
         Resolution|FIXED                       |

--- Comment #9 from Uros Bizjak <ubizjak at gmail dot com> 2012-05-14 18:13:50 UTC ---
(In reply to comment #8)
> Fixed.

This fix is not optimal, for the testcase we generate:

        movsd   (%rax), %xmm0
        movhpd  8(%rax), %xmm0
        movupd  %xmm0, -16(%rbp)
        movapd  -16(%rbp), %xmm0

So, we move (unaligned!) memory to a register, and then use movupd to store to
aligned stack slot. Luckily, gcc figures that the load is from unaligned memory
and generates movsd/movhpd combo.

The intention was to generate:

        movupd  (%rax), %xmm0
        movapd  %xmm0, -16(%rbp)
        movapd  -16(%rbp), %xmm0

So, we don't want a fixup in the expander, but we should always load to a
register for "load" builtin class. The patch should be reverted and following
patch should be applied instead:

Index: i386.c
===================================================================
--- i386.c      (revision 187465)
+++ i386.c      (working copy)
@@ -29472,8 +29472,8 @@ ix86_expand_special_args_builtin (const struct bui
       arg_adjust = 0;
       if (optimize
          || target == 0
-         || GET_MODE (target) != tmode
-         || !insn_p->operand[0].predicate (target, tmode))
+         || !register_operand (target, tmode)
+         || GET_MODE (target) != tmode)
        target = gen_reg_rtx (tmode);
     }

I will undo the (arguably, small) damage in all release branches.

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[uros at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

--- Comment #10 from uros at gcc dot gnu.org 2012-05-14 21:28:11 UTC ---
Author: uros
Date: Mon May 14 21:28:07 2012
New Revision: 187481

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=187481
Log:
    PR target/46098
    * config/i386/i386.c (ix86_expand_special_args_builtin): Always
    generate target register for "load" class builtins.

    Revert:
    2010-10-22  Uros Bizjak  <ubizjak@gmail.com>

    PR target/46098
    * config/i386/sse.md (*avx_movu<ssemodesuffix><avxmodesuffix>):
    Rename from avx_movu<ssemodesuffix><avxmodesuffix>.
    (avx_movu<ssemodesuffix><avxmodesuffix>): New expander.
    (*<sse>_movu<ssemodesuffix>): Rename from <sse>_movu<ssemodesuffix>.
    (<sse>_movu<ssemodesuffix>): New expander.
    (*avx_movdqu<avxmodesuffix>): Rename from avx_movdqu<avxmodesuffix>.
    (avx_movdqu<avxmodesuffix>): New expander.
    (*sse2_movdqu): Rename from sse2_movdqu.
    (sse2_movdqu): New expander.

testsuite/ChangeLog:

    * gcc.target/i386/avx256-unaligned-load-[1234].c: Update scan strings.
    * gcc.target/i386/avx256-unaligned-store-[1234].c: Ditto.


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386.c
    trunk/gcc/config/i386/sse.md
    trunk/gcc/testsuite/ChangeLog
    trunk/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
    trunk/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
    trunk/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c
    trunk/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
    trunk/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
    trunk/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
    trunk/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c
    trunk/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[uros at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

--- Comment #11 from uros at gcc dot gnu.org 2012-05-14 21:30:27 UTC ---
Author: uros
Date: Mon May 14 21:30:23 2012
New Revision: 187482

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=187482
Log:
    PR target/46098
    * config/i386/i386.c (ix86_expand_special_args_builtin): Always
    generate target register for "load" class builtins.

    Revert:
    2010-10-22  Uros Bizjak  <ubizjak@gmail.com>

    PR target/46098
    * config/i386/sse.md (*avx_movu<ssemodesuffix><avxmodesuffix>):
    Rename from avx_movu<ssemodesuffix><avxmodesuffix>.
    (avx_movu<ssemodesuffix><avxmodesuffix>): New expander.
    (*<sse>_movu<ssemodesuffix>): Rename from <sse>_movu<ssemodesuffix>.
    (<sse>_movu<ssemodesuffix>): New expander.
    (*avx_movdqu<avxmodesuffix>): Rename from avx_movdqu<avxmodesuffix>.
    (avx_movdqu<avxmodesuffix>): New expander.
    (*sse2_movdqu): Rename from sse2_movdqu.
    (sse2_movdqu): New expander.

testsuite/ChangeLog:

    * gcc.target/i386/avx256-unaligned-load-[1234].c: Update scan strings.
    * gcc.target/i386/avx256-unaligned-store-[1234].c: Ditto.


Modified:
    branches/gcc-4_7-branch/gcc/ChangeLog
    branches/gcc-4_7-branch/gcc/config/i386/i386.c
    branches/gcc-4_7-branch/gcc/config/i386/sse.md
    branches/gcc-4_7-branch/gcc/testsuite/ChangeLog
   
branches/gcc-4_7-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
   
branches/gcc-4_7-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
   
branches/gcc-4_7-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c
   
branches/gcc-4_7-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
   
branches/gcc-4_7-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
   
branches/gcc-4_7-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
   
branches/gcc-4_7-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c
   
branches/gcc-4_7-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[uros at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

--- Comment #12 from uros at gcc dot gnu.org 2012-05-14 21:32:35 UTC ---
Author: uros
Date: Mon May 14 21:32:29 2012
New Revision: 187483

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=187483
Log:
    PR target/46098
    * config/i386/i386.c (ix86_expand_special_args_builtin): Always
    generate target register for "load" class builtins.

    Revert:
    2010-10-22  Uros Bizjak  <ubizjak@gmail.com>

    PR target/46098
    * config/i386/sse.md (*avx_movu<ssemodesuffix><avxmodesuffix>):
    Rename from avx_movu<ssemodesuffix><avxmodesuffix>.
    (avx_movu<ssemodesuffix><avxmodesuffix>): New expander.
    (*<sse>_movu<ssemodesuffix>): Rename from <sse>_movu<ssemodesuffix>.
    (<sse>_movu<ssemodesuffix>): New expander.
    (*avx_movdqu<avxmodesuffix>): Rename from avx_movdqu<avxmodesuffix>.
    (avx_movdqu<avxmodesuffix>): New expander.
    (*sse2_movdqu): Rename from sse2_movdqu.
    (sse2_movdqu): New expander.

testsuite/ChangeLog:

    * gcc.target/i386/avx256-unaligned-load-[1234].c: Update scan strings.
    * gcc.target/i386/avx256-unaligned-store-[1234].c: Ditto.


Modified:
    branches/gcc-4_6-branch/gcc/ChangeLog
    branches/gcc-4_6-branch/gcc/config/i386/i386.c
    branches/gcc-4_6-branch/gcc/config/i386/sse.md
    branches/gcc-4_6-branch/gcc/testsuite/ChangeLog
   
branches/gcc-4_6-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
   
branches/gcc-4_6-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
   
branches/gcc-4_6-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c
   
branches/gcc-4_6-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
   
branches/gcc-4_6-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
   
branches/gcc-4_6-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
   
branches/gcc-4_6-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c
   
branches/gcc-4_6-branch/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[uros at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

--- Comment #13 from uros at gcc dot gnu.org 2012-05-14 21:35:20 UTC ---
Author: uros
Date: Mon May 14 21:35:16 2012
New Revision: 187484

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=187484
Log:
    PR target/46098
    * config/i386/i386.c (ix86_expand_special_args_builtin): Always
    generate target register for "load" class builtins.

    Revert:
    2010-10-22  Uros Bizjak  <ubizjak@gmail.com>

    PR target/46098
    * config/i386/sse.md (*avx_movu<ssemodesuffix><avxmodesuffix>):
    Rename from avx_movu<ssemodesuffix><avxmodesuffix>.
    (avx_movu<ssemodesuffix><avxmodesuffix>): New expander.
    (*<sse>_movu<ssemodesuffix>): Rename from <sse>_movu<ssemodesuffix>.
    (<sse>_movu<ssemodesuffix>): New expander.
    (*avx_movdqu<avxmodesuffix>): Rename from avx_movdqu<avxmodesuffix>.
    (avx_movdqu<avxmodesuffix>): New expander.
    (*sse2_movdqu): Rename from sse2_movdqu.
    (sse2_movdqu): New expander.


Modified:
    branches/gcc-4_5-branch/gcc/ChangeLog
    branches/gcc-4_5-branch/gcc/config/i386/i386.c
    branches/gcc-4_5-branch/gcc/config/i386/sse.md

[Bug target/46098] [4.5/4.6 Regression] ICE: in extract_insn, at recog.c:2100 with -msse3 -ffloat-store and __builtin_ia32_loadupd()

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46098

Uros Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
                URL|                            |http://gcc.gnu.org/ml/gcc-p
                   |                            |atches/2012-05/msg00951.htm
                   |                            |l
         Resolution|                            |FIXED

--- Comment #14 from Uros Bizjak <ubizjak at gmail dot com> 2012-05-14 21:40:19 UTC ---
Fixed again.