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From: "steven at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/46793] -fschedule-insns causes ICE in compiling zlib/trees.c
Date: Fri, 03 Dec 2010 21:05:00 -0000	[thread overview]
Message-ID: <bug-46793-4-p6mrxPsfJe@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-46793-4@http.gcc.gnu.org/bugzilla/>

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46793

--- Comment #3 from Steven Bosscher <steven at gcc dot gnu.org> 2010-12-03 21:05:46 UTC ---
The bug is in the architecture, not in the scheduling pass. You cannot expect
scheduling before register allocation to always yield code that you can
register-allocate with just 3 general registers available.

Enabling it only for AMD64 is not a work-around, it's the only proper thing to
do if you want to enable the pre-RA scheduling pass by default.

And there is still -fsched-pressure that you could try.

But I doubt you will get a patch approved to enable scheduling for 32-bits
ix86. The failure you are seeing can be triggered quite easily even _without_
scheduling enabled. Just search bugzilla for all the "unable to find spill
register" bugs on i386, this one is far from unique.


  parent reply	other threads:[~2010-12-03 21:05 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-12-03 20:26 [Bug rtl-optimization/46793] New: " changpeng.fang at amd dot com
2010-12-03 20:37 ` [Bug rtl-optimization/46793] " steven at gcc dot gnu.org
2010-12-03 20:52 ` changpeng.fang at amd dot com
2010-12-03 21:05 ` steven at gcc dot gnu.org [this message]
2010-12-03 21:24 ` changpeng.fang at amd dot com
2010-12-03 23:05 ` joseph at codesourcery dot com

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