From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29633 invoked by alias); 25 Jan 2011 09:43:22 -0000 Received: (qmail 29625 invoked by uid 22791); 25 Jan 2011 09:43:22 -0000 X-SWARE-Spam-Status: No, hits=-2.7 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00,TW_BL,TW_CB,TW_MV X-Spam-Check-By: sourceware.org Received: from localhost (HELO gcc.gnu.org) (127.0.0.1) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 25 Jan 2011 09:43:15 +0000 From: "carrot at google dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/47454] New: registers are not allocated according to its preferred order X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: carrot at google dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: Message-ID: X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Date: Tue, 25 Jan 2011 09:49:00 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2011-01/txt/msg02581.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47454 Summary: registers are not allocated according to its preferred order Product: gcc Version: 4.6.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: rtl-optimization AssignedTo: unassigned@gcc.gnu.org ReportedBy: carrot@google.com Target: arm-linux-androideabi Created attachment 23115 --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=23115 testcase The attached test case is extracted from zlib, when compiled by gcc4.6 with options -march=armv7-a -mthumb -Os, I got the following code push {r4, r5, r6, r7, r8, lr} mov r6, r0 mov r4, r1 cmp r0, #0 beq .L2 ldr r5, [r0, #0] cmp r5, #0 beq .L2 cmp r1, #0 bge .L3 negs r4, r1 movs r7, #0 b .L4 .L3: asrs r7, r1, #4 adds r7, r7, #1 cmp r1, #47 it le andle r4, r1, #15 .L4: adds r3, r4, #0 sub r8, r4, #8 it ne movne r3, #1 cmp r8, #7 ite ls movls r8, #0 andhi r8, r3, #1 cmp r8, #0 bne .L2 ldr r1, [r5, #8] cbz r1, .L5 ldr r3, [r5, #4] cmp r3, r4 beq .L5 ldr r3, [r6, #4] ldr r0, [r6, #8] blx r3 str r8, [r5, #8] .L5: str r7, [r5, #0] mov r0, r6 str r4, [r5, #4] pop {r4, r5, r6, r7, r8, lr} b inflateReset .L2: mvn r0, #1 pop {r4, r5, r6, r7, r8, pc} Note that register r8 is used many times, but register r2 is never used. In thumb2 r8 is high register, its usage will cause 32bit instructions. If we replace r8 with r2, a lot of code size will be reduced in this case. In arm.h REG_ALLOC_ORDER is defined as 3, 2, 1, 0, 12, 14, 4, 5, 6, 7, 8, 10, 9, 11, 13, 15 ... We can see that r2 should be used before r8, but the result is not.