[Bug c/47825] New: SSE bitwise operations on floats work -g, fail -O3

[Bug c/47825] New: SSE bitwise operations on floats work -g, fail -O3

[cck0011 at yahoo dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47825

           Summary: SSE bitwise operations on floats work -g, fail -O3
           Product: gcc
           Version: 4.3.2
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: cck0011@yahoo.com


Created attachment 23413
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=23413
.i file

Hi folks,

  I'm trying the vec_sel() example using SSE (bitwise and, or, andnot) to
select bits from two vectors to build a third. It works under -g, but fails
under -O3.
What am I missing?

thanks.


gcc -v
Using built-in specs.
Target: i386-redhat-linux
Configured with: ../configure --prefix=/usr --mandir=/usr/share/man
--infodir=/usr/share/info --with-bugurl=http://bugzilla.redhat.com/bugzilla
--enable-bootstrap --enable-shared --enable-threads=posix
--enable-checking=release --with-system-zlib --enable-__cxa_atexit
--disable-libunwind-exceptions
--enable-languages=c,c++,objc,obj-c++,java,fortran,ada --enable-java-awt=gtk
--disable-dssi --enable-plugin
--with-java-home=/usr/lib/jvm/java-1.5.0-gcj-1.5.0.0/jre
--enable-libgcj-multifile --enable-java-maintainer-mode
--with-ecj-jar=/usr/share/java/eclipse-ecj.jar --disable-libjava-multilib
--with-cpu=generic --build=i386-redhat-linux
Thread model: posix
gcc version 4.3.2 20081105 (Red Hat 4.3.2-7) (GCC)

works under:
  cc -g -o setel setel.c  -msse -mmmx -pedantic -Wall

fails under:
  cc -O3 -o setel setel.c  -msse -mmmx -pedantic -Wall


.i file attached

[Bug c/47825] SSE bitwise operations on floats work -g, fail -O3

[rguenth at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47825

Richard Guenther <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|                            |INVALID

--- Comment #1 from Richard Guenther <rguenth at gcc dot gnu.org> 2011-02-20 17:22:58 UTC ---
You are violating aliasing rules.  Add may_alias to the attributes of your
float array.

[Bug c/47825] SSE bitwise operations on floats work -g, fail -O3

[cck0011 at yahoo dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47825

--- Comment #2 from cck0011 at yahoo dot com 2011-02-20 17:35:56 UTC ---
Created attachment 23414
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=23414
source file with _may_alias_ attribute added

Hi Richard,

  thanks for replying. I added _may_alias_; no change in results.

  What am I missing?

  Source attached.

Thanks!

[Bug c/47825] SSE bitwise operations on floats work -g, fail -O3

[rguenth at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47825

--- Comment #3 from Richard Guenther <rguenth at gcc dot gnu.org> 2011-02-20 17:42:41 UTC ---
Probably the same on maskarray.  You should also try to update GCC to
4.3.5.

[Bug c/47825] SSE bitwise operations on floats work -g, fail -O3

[cck0011 at yahoo dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47825

--- Comment #4 from cck0011 at yahoo dot com 2011-02-20 18:22:46 UTC ---
(In reply to comment #3)
> Probably the same on maskarray.  You should also try to update GCC to
> 4.3.5.

Hi Richard,

  added to maskarray as well: no change in results. Adding option
-fno-strict-aliasing fixes it as well. I'm confused: since _mm_store_ps
explicitly copies into floatarray why is aliasing an issue?

thanks!

[Bug target/47825] SSE bitwise operations on floats work -g, fail -O3

[rguenth at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47825

Richard Guenther <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|                            |x86_64-*-*
             Status|RESOLVED                    |REOPENED
   Last reconfirmed|                            |2011.02.21 10:40:58
                 CC|                            |hjl at gcc dot gnu.org
          Component|c                           |target
         Resolution|INVALID                     |
     Ever Confirmed|0                           |1

--- Comment #5 from Richard Guenther <rguenth at gcc dot gnu.org> 2011-02-21 10:40:58 UTC ---
The issue is that maskarray is initialized as array of ints but then you
load it as array of floats, the scheduler re-orders those so you see
a load from uninitialized stack:

test_setelement:
.LFB546:
        subq    $40, %rsp
.LCFI0:
        movaps  16(%rsp), %xmm0
        movl    $0, 16(%rsp)
        movl    $0, 20(%rsp)
        movaps  %xmm0, %xmm1
        andnps  .LC1(%rip), %xmm0
        movl    $0, 24(%rsp)
        movl    $-1, 28(%rsp)
...

what is a bit inconsistent is that for mm_load_pd we use a type that
allows aliasing:

/* The Intel API is flexible enough that we must allow aliasing with other
   vector types, and their scalar components.  */
typedef long long __m128i __attribute__ ((__vector_size__ (16),
__may_alias__));
typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__));

...

/* Load two DPFP values from P.  The address must be 16-byte aligned.  */
extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
_mm_load_pd (double const *__P)
{
  return *(__m128d *)__P;
}

but for mm_load_ps we don't:

/* Internal data types for implementing the intrinsics.  */
typedef float __v4sf __attribute__ ((__vector_size__ (16)));

...

/* Load four SPFP values from P.  The address must be 16-byte aligned.  */
extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
_mm_load_ps (float const *__P)
{
  return (__m128) *(__v4sf *)__P;
}


re-opening to investigate that.  HJ, are the SSE1 intrinsics not
aliasing in the Intel API?  The above snippets are from trunk.

[Bug target/47825] SSE bitwise operations on floats work -g, fail -O3

[hjl.tools at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47825

H.J. Lu <hjl.tools at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|hjl at gcc dot gnu.org      |hjl.tools at gmail dot com,
                   |                            |ubizjak at gmail dot com

--- Comment #6 from H.J. Lu <hjl.tools at gmail dot com> 2011-02-21 13:53:02 UTC ---
(In reply to comment #5)

> /* Load four SPFP values from P.  The address must be 16-byte aligned.  */
> extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__,
> __artificial__))
> _mm_load_ps (float const *__P)
> {
>   return (__m128) *(__v4sf *)__P;
> }
> 
> 
> re-opening to investigate that.  HJ, are the SSE1 intrinsics not
> aliasing in the Intel API?  The above snippets are from trunk.

It is a bug and should be fixed.

[Bug target/47825] SSE bitwise operations on floats work -g, fail -O3

[cck0011 at yahoo dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47825

--- Comment #7 from cck0011 at yahoo dot com 2011-02-22 00:54:17 UTC ---
(In reply to comment #5)
> The issue is that maskarray is initialized as array of ints but then you
> load it as array of floats, the scheduler re-orders those so you see
> a load from uninitialized stack:
> 
[looks puzzled; reads info page for gcc -fstrict-aliasing for the N + 1th time;
sudden look of comprehension dawns...]

"taking a pointer and casting gives undefined result..."

 Thank you Richard. That makes sense now given the context... -)

Thanks folks!

[Bug target/47825] SSE bitwise operations on floats work -g, fail -O3

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=47825

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
   Target Milestone|---                         |7.0
             Status|REOPENED                    |RESOLVED

--- Comment #8 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Fixed for GCC 7+ by r7-2885.
@@ -921,14 +924,14 @@ _mm_load_ps1 (float const *__P)
 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
 _mm_load_ps (float const *__P)
 {
-  return (__m128) *(__v4sf *)__P;
+  return *(__m128 *)__P;
 }