From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4116 invoked by alias); 1 Mar 2011 06:44:55 -0000 Received: (qmail 4106 invoked by uid 22791); 1 Mar 2011 06:44:55 -0000 X-SWARE-Spam-Status: No, hits=-2.8 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from localhost (HELO gcc.gnu.org) (127.0.0.1) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 01 Mar 2011 06:44:50 +0000 From: "carrot at google dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/47920] strange code generated for expression (a+7)/8 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: carrot at google dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Date: Tue, 01 Mar 2011 06:44:00 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2011-03/txt/msg00012.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47920 --- Comment #3 from Carrot 2011-03-01 06:44:47 UTC --- (In reply to comment #1) > Presumably because arithmetic right-shift by 3 isn't the same as a division by > 8 when (a+7) is negative. Changing the types to unsigned gives the code you > want. You are right. Right shift and division are different for negative numbers. Thumb1 uses a different code sequence since it doesn't support conditional execution t08: add r0, r0, #7 asr r3, r0, #31 lsr r3, r3, #29 add r0, r3, r0 asr r0, r0, #3 bx lr If we use the similar code sequence in thumb2 we can reduce one instruction because the logical shift and the following add can be merged into one instruction t08: add r0, r0, #7 asr r3, r0, #31 add r0, r0, r3, LSR #29 asr r0, r0, #3 bx lr I wonder if this will be faster.