From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26056 invoked by alias); 22 Jun 2011 19:01:37 -0000 Received: (qmail 26042 invoked by uid 22791); 22 Jun 2011 19:01:37 -0000 X-SWARE-Spam-Status: No, hits=-2.7 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00,TW_PX X-Spam-Check-By: sourceware.org Received: from localhost (HELO gcc.gnu.org) (127.0.0.1) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 22 Jun 2011 19:01:22 +0000 From: "m.k.edwards at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/48126] arm_output_sync_loop: misplaced memory barrier, missing clrex / dummy strex X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: m.k.edwards at gmail dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Date: Wed, 22 Jun 2011 19:01:00 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2011-06/txt/msg01994.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48126 --- Comment #6 from Michael K. Edwards 2011-06-22 19:00:54 UTC --- (In reply to comment #5) > If I understand correctly however most cases wouldn't need it - I think most > cases are use the compare&swap to take some form of lock, and then once you > know you have the lock go and do your accesses - and in that case the ordering > is guaranteed, where as if you couldn't take the lock you wouldn't use the > subsequent access anyway. Yes, that fits my understanding. It's only when you actually use the compare-and-swap as a compare-and-swap that you can get bit. I expect that it is quite hard to hit this in the 32-bit case, but with your 64-bit atomics and a dual-core system it should be a little easier to expose. I have an implementation of Michael-Scott lock-free queues (which rely on applying DCAS to a counter+pointer), in which I currently use the assembly cmpxchg64 equivalent we discussed; I'll adapt it to use the GCC intrinsic and re-test.