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From: "marcus.shawcroft at arm dot com" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/48126] arm_output_sync_loop: misplaced memory barrier, missing clrex / dummy strex
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48126

Marcus Shawcroft <marcus.shawcroft at arm dot com> changed:

           What    |Removed                     |Added
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                 CC|                            |marcus.shawcroft at arm dot
                   |                            |com

--- Comment #1 from Marcus Shawcroft <marcus.shawcroft at arm dot com> 2011-03-17 16:14:36 UTC ---
The code sequence in question looks like this:
    dmb     sy
1:
    ldrex   r0, ...
    cmp     r0, r1
    bne     2f
    strex   r4, r2, ..
    teq     r4, #0 
    bne     1b
    dmb     sy
2:

The ARM Architecture reference manual (section 3.4.5) requires that
there are no explicit memory references between the LDREX and the
STREX, this requirement does not extended to speculative loads in
branch shadows.

An LDREX without a following STREX is explicilty permitted by the
reference manual (section 3.4.5).

The CLREX instruction is provided for use by context switch code in
order to prevent a false positive STREX following a context switch
(section 3.4.4). The inclusion of a CLREX instruction in the above
fragment is not required by the ARM architecture reference manual.