[Bug rtl-optimization/48345] New: [4.7 Regression] [SH] Invalid float register allocated

[Bug rtl-optimization/48345] New: [4.7 Regression] [SH] Invalid float register allocated

[kkojima at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48345

           Summary: [4.7 Regression] [SH] Invalid float register allocated
           Product: gcc
           Version: 4.7.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: kkojima@gcc.gnu.org


sh4-unknown-linux-gnu fails to build on trunk revision 171649
during compiling libgfortran.  The compiler generates invalid
float instructions using wrong drN registers.  A typical
example in the C testsuite is gcc.c-torture/compile/pr34091.c
with -O2 which produces the instruction like

    fadd    dr14,dr3

which is reproduced on sh-elf -m4 -ml too.
On SH with fpu, only even dr registers are valid double
float registers, though the register allocator allocates dr3
which is invalid.
.ira dump says that the problematic hard reg 67 corresponding
dr3 is allocated:

    Secondary allocation: assign hard reg 67 to reg 757

where reg 757 is a DFmode register.
It seems that ira-color.c:assign_hard_reg chooses a register
of which corresponding bit of ira_prohibited_class_mode_regs
[FP_REGS][DFmode] is set.  The patch below looks to work for me,
though I'm suspecting the real problem is in the target side.

--- ORIG/trunk/gcc/ira-color.c    2011-03-29 10:08:17.000000000 +0900
+++ LOCAL/trunk/gcc/ira-color.c    2011-03-29 15:09:06.000000000 +0900
@@ -1692,6 +1692,9 @@ assign_hard_reg (ira_allocno_t a, bool r
       && FIRST_STACK_REG <= hard_regno && hard_regno <= LAST_STACK_REG)
     continue;
 #endif
+      if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[aclass][mode],
+                 hard_regno))
+    continue;
       if (! check_hard_reg_p (a, hard_regno,
                   conflicting_regs, profitable_hard_regs))
     continue;

[Bug rtl-optimization/48345] [4.7 Regression] [SH] Invalid float register allocated

[kkojima at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48345

--- Comment #1 from Kazumoto Kojima <kkojima at gcc dot gnu.org> 2011-03-29 22:45:59 UTC ---
It looks that the above patch also fixes the wrong register allocation
in PR48336.

[Bug rtl-optimization/48345] [4.7 Regression] [SH] Invalid float register allocated

[vmakarov at redhat dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48345

--- Comment #2 from Vladimir Makarov <vmakarov at redhat dot com> 2011-03-29 23:59:08 UTC ---
(In reply to comment #0)
> 
> It seems that ira-color.c:assign_hard_reg chooses a register
> of which corresponding bit of ira_prohibited_class_mode_regs
> [FP_REGS][DFmode] is set.  The patch below looks to work for me,
> though I'm suspecting the real problem is in the target side.
> 
> --- ORIG/trunk/gcc/ira-color.c    2011-03-29 10:08:17.000000000 +0900
> +++ LOCAL/trunk/gcc/ira-color.c    2011-03-29 15:09:06.000000000 +0900
> @@ -1692,6 +1692,9 @@ assign_hard_reg (ira_allocno_t a, bool r
>        && FIRST_STACK_REG <= hard_regno && hard_regno <= LAST_STACK_REG)
>      continue;
>  #endif
> +      if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[aclass][mode],
> +                 hard_regno))
> +    continue;
>        if (! check_hard_reg_p (a, hard_regno,
>                    conflicting_regs, profitable_hard_regs))
>      continue;

The patch is ok for me.  This code was lost accidentally on ira-improv branch.

Could you commit the patch (of course with a proper changelog entry).  I am
approving the patch.

Thanks.

[Bug rtl-optimization/48345] [4.7 Regression] [SH] Invalid float register allocated

[kkojima at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48345

--- Comment #3 from Kazumoto Kojima <kkojima at gcc dot gnu.org> 2011-03-30 00:28:32 UTC ---
Thanks!  Is

    PR rtl-optimization/48345
    * ira-color.c (assign_hard_reg): Skip prohibited hard registers
    for given class and mode.

OK for ChangeLog?

[Bug rtl-optimization/48345] [4.7 Regression] [SH] Invalid float register allocated

[vmakarov at redhat dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48345

--- Comment #4 from Vladimir Makarov <vmakarov at redhat dot com> 2011-03-30 00:49:50 UTC ---

(In reply to comment #3)
> Thanks!  Is
> 
>     PR rtl-optimization/48345
>     * ira-color.c (assign_hard_reg): Skip prohibited hard registers
>     for given class and mode.
> 
> OK for ChangeLog?

Sorry, Kazumoto.  Please do not commit the patch.  The problem is a bit more
deeper than I thought.

The profitable hard regs should exclude prohibited hard regs for given mode. 
It is true for major allocation.  The wrong register is assigned during
secondary allocation (after flattening IRA IR or during reload) where
profitable hard register is not defined properly.  So the fix should contain
the code for proper setting profitable hard regs.

I'll create a patch soon.

Sorry again for jumping to a wrong conclusion.

[Bug rtl-optimization/48345] [4.7 Regression] [SH] Invalid float register allocated

[vmakarov at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48345

--- Comment #5 from Vladimir Makarov <vmakarov at gcc dot gnu.org> 2011-03-30 02:11:11 UTC ---
Author: vmakarov
Date: Wed Mar 30 02:11:04 2011
New Revision: 171713

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=171713
Log:
2011-03-29  Vladimir Makarov  <vmakarov@redhat.com>

    PR target/48336
    PR middle-end/48342
    PR rtl-optimization/48345
    * ira-color.c (setup_conflict_profitable_regs): Exclude prohibited
    hard regs for given mode from profitable regs when doing secondary
    allocation.


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/ira-color.c

[Bug rtl-optimization/48345] [4.7 Regression] [SH] Invalid float register allocated

[kkojima at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48345

Kazumoto Kojima <kkojima at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|                            |FIXED

--- Comment #6 from Kazumoto Kojima <kkojima at gcc dot gnu.org> 2011-03-30 03:45:17 UTC ---
Fixed.  Thanks for explanations and a very quick fix.

[Bug rtl-optimization/48345] [4.7 Regression] [SH] Invalid float register allocated

[rguenth at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48345

Richard Guenther <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |4.7.0