From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14922 invoked by alias); 30 Mar 2011 06:51:54 -0000 Received: (qmail 14911 invoked by uid 22791); 30 Mar 2011 06:51:53 -0000 X-SWARE-Spam-Status: No, hits=-2.9 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from localhost (HELO gcc.gnu.org) (127.0.0.1) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 30 Mar 2011 06:51:48 +0000 From: "krebbel at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug middle-end/48353] New: Bootstrap fail due to invalid register pair being assigned to pseudo X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: middle-end X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: krebbel at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: Message-ID: X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Date: Wed, 30 Mar 2011 07:18:00 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2011-03/txt/msg03128.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48353 Summary: Bootstrap fail due to invalid register pair being assigned to pseudo Product: gcc Version: 4.7.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: middle-end AssignedTo: unassigned@gcc.gnu.org ReportedBy: krebbel@gcc.gnu.org Created attachment 23811 --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=23811 testcase Compiling the attached testcase with -O2 produces an invalid divide instruction: dsgfr %r7,%r1 The first parameter needs to an even numbered register. from ira dump: Try Assign 103(a10), cost=226: reassign to 7 changing reg in insn 50 Register 93 now in 3. Register 103 now in 7. (insn 50 40 62 4 (set (reg:TI 7 %r7 [103]) (ior:TI (ashift:TI (zero_extend:TI (mod:DI (reg:DI 8 %r8 [99]) (sign_extend:DI (reg/v:SI 1 %r1 [orig:49 copy_nregs ] [49])))) (const_int 64 [0x40])) (zero_extend:TI (div:DI (reg:DI 8 %r8 [99]) (sign_extend:DI (reg/v:SI 1 %r1 [orig:49 copy_nregs ] [49])))))) t.c:32 380 {divmodtisi3} (nil))