[Bug middle-end/48366] New: [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[Bug middle-end/48366] New: [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[danglin at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

           Summary: [4.7 Regression] ICE in extract_constrain_insn_cached,
                    at recog.c:2024
           Product: gcc
           Version: 4.7.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: danglin@gcc.gnu.org
              Host: hppa64-hp-hpux11.11
            Target: hppa64-hp-hpux11.11
             Build: hppa64-hp-hpux11.11


Executing on host: /test/gnu/gcc/objdir/gcc/xgcc -B/test/gnu/gcc/objdir/gcc/  
-
O0  -w -c  -o 20010518-1.o
/test/gnu/gcc/gcc/gcc/testsuite/gcc.c-torture/compile
/20010518-1.c    (timeout = 300)
/test/gnu/gcc/gcc/gcc/testsuite/gcc.c-torture/compile/20010518-1.c: In function
'emit_reload_insns':
/test/gnu/gcc/gcc/gcc/testsuite/gcc.c-torture/compile/20010518-1.c:205:1:
error:
 insn does not satisfy its constraints:
(insn 554 553 555 (set (reg:DI 1 %r1)
        (reg:DI 50 %fr22 [285]))
/test/gnu/gcc/gcc/gcc/testsuite/gcc.c-torture/c
ompile/20010518-1.c:167 120 {*pa.md:4101}
     (nil))
/test/gnu/gcc/gcc/gcc/testsuite/gcc.c-torture/compile/20010518-1.c:205:1:
intern
al compiler error: in extract_constrain_insn_cached, at recog.c:2024

Numerous other similar testsuite falls, all at -O0.

-bash-3.2$ ./xgcc -B./ -v
Reading specs from ./specs
COLLECT_GCC=./xgcc
COLLECT_LTO_WRAPPER=./lto-wrapper
Target: hppa64-hp-hpux11.11
Configured with: ../gcc/configure --with-gnu-as --with-as=/opt/gnu64/bin/as
--with-ld=/usr/ccs/bin/ld --enable-shared --with-local-prefix=/opt/gnu64
--prefix=/opt/gnu64/gcc/gcc-4.6.0 --build=hppa64-hp-hpux11.11
--enable-threads=posix --disable-nls --with-gmp=/opt/gnu64/gcc/gcc-4.6.0
--with-libelf=/opt/gnu64 --enable-languages=c,c++,objc,obj-c++,fortran,lto
Thread model: posix
gcc version 4.7.0 20110330 (experimental) [trunk revision 171715] (GCC)

Probably, has to do with change in handling of cover classes.  It
is not possible to copy directly between GENERAL_REGS and FP_REGS
on PA.

[Bug middle-end/48366] [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[rguenth at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

Richard Guenther <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |4.7.0

[Bug middle-end/48366] [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[dave at hiauly1 dot hia.nrc.ca]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

--- Comment #1 from dave at hiauly1 dot hia.nrc.ca 2011-03-30 23:30:54 UTC ---
Attached .i and relevant rtl dumps.

[Bug target/48366] [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[danglin at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

John David Anglin <danglin at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|middle-end                  |target

--- Comment #4 from John David Anglin <danglin at gcc dot gnu.org> 2011-04-02 19:04:24 UTC ---
pa_secondary_reload doesn't handle copies to/from FP_REGS correctly.
We need an immediate general register on 64-bit targets.

[Bug target/48366] [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[danglin at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

--- Comment #5 from John David Anglin <danglin at gcc dot gnu.org> 2011-04-02 19:56:50 UTC ---
With pa_secondary_reload fixed, the following code is generated at -O0:

        subi 63,%r31,%r31
        std %r31,80(%r3)
        fldd 80(%r3),%fr22
        fstd %fr22,80(%r3)
        ldd 80(%r3),%r1
        mtsar %r1
        depdi,z 1,%sar,64,%r31

I don't know why reload generates such bad code.  The SAR shift amount
register is a special 5/6 bit register used for shift operations.
It can only be loaded from a general register.

We seem to have an output reload that causes the copy from r31
to fr22.  Then fr22 is copied back to general register r1.  Then
it is moved to the sar register.  Why did reload generate this
code?  r31 could have been moved directly.  I would have thought
the costs in moving r31 to fr22 and back to r1 would have inhibited
this alternative relative to directly moving r31 to the sar.

[Bug target/48366] [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[vmakarov at redhat dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

Vladimir Makarov <vmakarov at redhat dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |vmakarov at redhat dot com

--- Comment #6 from Vladimir Makarov <vmakarov at redhat dot com> 2011-04-03 18:18:03 UTC ---
John, thanks for reporting the PR and working on it.

I guess that the last patch (for pr48380) I sent should solve the problem too.
Unfortunately, I did not get an approval for the patch yet.

I'd recommend you to check the patch first because it might save you a lot of
time because the problem occurs in reload and it is hard to analyze the reload.
 But the real reason of the problem is in wrong IRA directions.

[Bug target/48366] [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[dave at hiauly1 dot hia.nrc.ca]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

--- Comment #7 from dave at hiauly1 dot hia.nrc.ca 2011-04-03 18:37:07 UTC ---
> I guess that the last patch (for pr48380) I sent should solve the problem too.
> Unfortunately, I did not get an approval for the patch yet.

I'll try it if it isn't install by the time I get to a retest.

>  But the real reason of the problem is in wrong IRA directions.

The wrong IRA directions have exposed backend problems in handling
reloads for the shift amount register.  I think I have a patch to
correct these issues.  Testing the change now.

Thanks,
Dave

[Bug target/48366] [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[dave at hiauly1 dot hia.nrc.ca]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

--- Comment #8 from dave at hiauly1 dot hia.nrc.ca 2011-04-04 00:34:48 UTC ---
On Sun, 03 Apr 2011, John David Anglin wrote:

> > I guess that the last patch (for pr48380) I sent should solve the problem too.
> > Unfortunately, I did not get an approval for the patch yet.
> 
> I'll try it if it isn't install by the time I get to a retest.

../../gcc/gcc/ira-emit.c: In function `emit_move_list':
../../gcc/gcc/ira-emit.c:938:8: error: comparison between signed and unsigned
integer expressions [-Werror=sign-compare]

Dave

[Bug target/48366] [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[danglin at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

--- Comment #9 from John David Anglin <danglin at gcc dot gnu.org> 2011-04-08 16:21:47 UTC ---
Author: danglin
Date: Fri Apr  8 16:21:39 2011
New Revision: 172197

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=172197
Log:
    PR target/48366
    * config/pa/pa.c (hppa_register_move_cost): Increase to 18 cost of
    move from floating point to shift amount register .
    (emit_move_sequence): Remove secondary reload support for floating
    point to shift amount amount register copies.
    (pa_secondary_reload): Return GENERAL_REGS for floating point/shift
    amount register copies.
    * config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): For shift amount
    register, return false if mode isn't a scalar integer mode.
    * config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Likewise.


Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/pa/pa.c
    trunk/gcc/config/pa/pa32-regs.h
    trunk/gcc/config/pa/pa64-regs.h

[Bug target/48366] [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[danglin at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

John David Anglin <danglin at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|                            |FIXED

--- Comment #10 from John David Anglin <danglin at gcc dot gnu.org> 2011-04-09 15:21:21 UTC ---
Fixed on trunk.

[Bug target/48366] [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[danglin at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

--- Comment #11 from John David Anglin <danglin at gcc dot gnu.org> 2011-04-13 22:37:02 UTC ---
Author: danglin
Date: Wed Apr 13 22:36:59 2011
New Revision: 172400

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=172400
Log:
    Backport from mainline:
    2011-04-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

    PR target/48366
    * config/pa/pa.c (hppa_register_move_cost): Increase to 18 cost of
    move from floating point to shift amount register .
    (emit_move_sequence): Remove secondary reload support for floating
    point to shift amount amount register copies.
    (pa_secondary_reload): Return GENERAL_REGS for floating point/shift
    amount register copies.
    * config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): For shift amount
    register, return false if mode isn't a scalar integer mode.
    * config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Likewise.


Modified:
    branches/gcc-4_6-branch/gcc/ChangeLog
    branches/gcc-4_6-branch/gcc/config/pa/pa.c
    branches/gcc-4_6-branch/gcc/config/pa/pa32-regs.h
    branches/gcc-4_6-branch/gcc/config/pa/pa64-regs.h

[Bug target/48366] [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[danglin at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

--- Comment #12 from John David Anglin <danglin at gcc dot gnu.org> 2011-04-16 17:10:35 UTC ---
Author: danglin
Date: Sat Apr 16 17:10:29 2011
New Revision: 172589

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=172589
Log:
    * config/pa/pa.h (REGISTER_MOVE_COST): Increase to 18 cost of
    move from floating point to shift amount register.

    Backport from mainline:
    2011-04-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

    PR target/48366
    * config/pa/pa.c (emit_move_sequence): Remove secondary reload
    support for floating point to shift amount amount register copies.
    (pa_secondary_reload): Return GENERAL_REGS for floating point/shift
    amount register copies.
    * config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): For shift amount
    register, return false if mode isn't a scalar integer mode.
    * config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Likewise.


Modified:
    branches/gcc-4_5-branch/gcc/ChangeLog
    branches/gcc-4_5-branch/gcc/config/pa/pa.c
    branches/gcc-4_5-branch/gcc/config/pa/pa.h
    branches/gcc-4_5-branch/gcc/config/pa/pa32-regs.h
    branches/gcc-4_5-branch/gcc/config/pa/pa64-regs.h

[Bug target/48366] [4.7 Regression] ICE in extract_constrain_insn_cached, at recog.c:2024

[danglin at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48366

--- Comment #13 from John David Anglin <danglin at gcc dot gnu.org> 2011-04-19 14:21:24 UTC ---
Author: danglin
Date: Tue Apr 19 14:21:18 2011
New Revision: 172710

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=172710
Log:
    * config/pa/pa.h (REGISTER_MOVE_COST): Increase to 18 cost of
    move from floating point to shift amount register.

    Backport from mainline:
    2011-04-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

    PR target/48366
    * config/pa/pa.c (emit_move_sequence): Remove secondary reload
    support for floating point to shift amount amount register copies.
    (pa_secondary_reload): Return GENERAL_REGS for floating point/shift
    amount register copies.
    * config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): For shift amount
    register, return false if mode isn't a scalar integer mode.
    * config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Likewise.


Modified:
    branches/gcc-4_4-branch/gcc/ChangeLog
    branches/gcc-4_4-branch/gcc/config/pa/pa.c
    branches/gcc-4_4-branch/gcc/config/pa/pa.h
    branches/gcc-4_4-branch/gcc/config/pa/pa32-regs.h
    branches/gcc-4_4-branch/gcc/config/pa/pa64-regs.h