From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14909 invoked by alias); 10 Jun 2011 02:54:13 -0000 Received: (qmail 14900 invoked by uid 22791); 10 Jun 2011 02:54:12 -0000 X-SWARE-Spam-Status: No, hits=-2.7 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from localhost (HELO gcc.gnu.org) (127.0.0.1) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 10 Jun 2011 02:53:56 +0000 From: "hp at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/49357] New: [4.7 Regression] register allocation worse X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: hp at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: Message-ID: X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Date: Fri, 10 Jun 2011 02:54:00 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2011-06/txt/msg00827.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49357 Summary: [4.7 Regression] register allocation worse Product: gcc Version: 4.7.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: rtl-optimization AssignedTo: unassigned@gcc.gnu.org ReportedBy: hp@gcc.gnu.org Host: x86_64-unknown-linux-gnu Target: cris-axis-elf Compare the prologue for the test-case in attachment 24471 to PR49154 and compiled according to those instructions, between 4.3.3 (everything before the first "add"): subq 4,$sp move $srp,[$sp] subq 12,$sp movem $r2,[$sp] move.d $r10,$r2 move.d $r10,$r9 move.d $r11,$r10 to that of trunk at r174114 as well as r174870: subq 4,$sp move $srp,[$sp] subq 16,$sp movem $r3,[$sp] subq 4,$sp move.d $r8,[$sp] move.d $r10,$r8 move.d $r11,$r9 So, we have a regression from 3 to 5 registers, and with a hole compared to reg_alloc_order. Note that the source uses DFmode and DImode and derived unions; at a glance "normal" code is less affected. Building on a 32-bit host seems to aggravate the situation. Just put here as a note for the time being.