From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14270 invoked by alias); 5 Jul 2011 12:19:34 -0000 Received: (qmail 14259 invoked by uid 22791); 5 Jul 2011 12:19:29 -0000 X-SWARE-Spam-Status: No, hits=-2.7 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from localhost (HELO gcc.gnu.org) (127.0.0.1) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 05 Jul 2011 12:19:15 +0000 From: "sebastian.huber@embedded-brains.de" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/49641] New: [ARM] Wrong code for ARMv4T and stmia X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: sebastian.huber@embedded-brains.de X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: Message-ID: X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Date: Tue, 05 Jul 2011 12:19:00 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2011-07/txt/msg00303.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49641 Summary: [ARM] Wrong code for ARMv4T and stmia Product: gcc Version: 4.6.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target AssignedTo: unassigned@gcc.gnu.org ReportedBy: sebastian.huber@embedded-brains.de Target: arm-rtemseabi4.11 Created attachment 24689 --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=24689 Sample code. The attached source code generates the following assembler code: 00000000 <_Watchdog_Handler_initialization>: 0: 2200 movs r2, #0 2: 4b06 ldr r3, [pc, #24] ; (1c <_Watchdog_Handler_initialization+0x1c>) 4: 601a str r2, [r3, #0] 6: 4b06 ldr r3, [pc, #24] ; (20 <_Watchdog_Handler_initialization+0x20>) 8: 601a str r2, [r3, #0] a: 4b06 ldr r3, [pc, #24] ; (24 <_Watchdog_Handler_initialization+0x24>) c: 601a str r2, [r3, #0] e: 4b06 ldr r3, [pc, #24] ; (28 <_Watchdog_Handler_initialization+0x28>) 10: 1d19 adds r1, r3, #4 12: c30e stmia r3!, {r1, r2, r3} 14: 4b05 ldr r3, [pc, #20] ; (2c <_Watchdog_Handler_initialization+0x2c>) 16: 1d19 adds r1, r3, #4 18: c30e stmia r3!, {r1, r2, r3} 1a: 4770 bx lr In particular it generates: stmia r3!, {r1, r2, r3} This instruction leads to UNPREDICTABLE behavior. According to "ARM Architecture Reference Manual, Issue I" we have in section "A7.1.57 STMIA", "Operand restrictions": "If is specified in : o If is the lowest-numbered register specified in , the original value of is stored. o Otherwise, the stored value of is UNPREDICTABLE." Since r3 is not the lowest-numbered register specified in {r1, r2, r3} the stored value of r3 is UNPREDICTABLE.