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Subject: [Bug target/49798] .quad instead of .long is used for address for x32
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49798

--- Comment #8 from H.J. Lu <hjl.tools at gmail dot com> 2011-07-21 16:03:20 UTC ---
(In reply to comment #7)
> IRA generates
> 
> (insn 13 3 18 2 (set (reg/v:DI 21 xmm0 [orig:63 v ] [63])
>         (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
> x.i:12 62 {*movdi_internal_rex64}
>      (expr_list:REG_EQUIV (symbol_ref:DI ("xxxx") [flags 0x40]  <var_decl
> 0x7f4068bbc140 xxxx>)
>         (nil)))
> 
> This requires zero-extending 32bit address to 64bit.

I am not sure how we can express it in constant pool beyond what
we have today.  I can add a new assembler directive, xquad, so that we do
something similar to

/* Target hook for assembling integer objects.  The sparc version has
   special handling for aligned DI-mode objects.  */

static bool
sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
{
  /* ??? We only output .xword's for symbols and only then in environments
     where the assembler can handle them.  */
  if (aligned_p && size == 8
      && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
    {
      if (TARGET_V9)
        {
          assemble_integer_with_op ("\t.xword\t", x);
          return true;
        }
      else
        {
          assemble_aligned_integer (4, const0_rtx);
          assemble_aligned_integer (4, x);
          return true;
        }
    }
  return default_assemble_integer (x, size, aligned_p);
}