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From: "pthaugen at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug rtl-optimization/49890] New: IRA spill with plenty of available registers
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49890

           Summary: IRA spill with plenty of available registers
           Product: gcc
           Version: 4.7.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
        AssignedTo: unassigned@gcc.gnu.org
        ReportedBy: pthaugen@gcc.gnu.org
                CC: vmakarov@gcc.gnu.org, bergner@gcc.gnu.org
              Host: powerpc64-linux
            Target: powerpc64-linux
             Build: powerpc64-linux


Vlad,
  Opening bz as you requested.  Background/detail can be found here:
http://gcc.gnu.org/ml/gcc/2011-05/msg00186.html.

Basically, following testcase compiled with gcc -S -m64 -O3 -mcpu=power7 causes
IRA to spill pseudo used for copy.

void foo(float *f1, float*f2) {
  *f1 = *f2;
}


**** Allocnos coloring:

  Loop 0 (parent -1, header bb0, depth 0)
    bbs: 2
    all: 0r120
    modified regnos: 120
    border:
    Pressure: NON_FLOAT_REGS=2
    Hard reg set forest:
      0:( 0 3-12 14-63 65 66 68-72 74 75 77-108)@0
      Spill a0(r120,l0)
Disposition:
    0:r120 l0   mem