[Bug rtl-optimization/51821] [4.5/4.6/4.7 Regression] 64bit > 32bit conversion produces incorrect results with optimizations

["ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51821

--- Comment #9 from Uros Bizjak <ubizjak at gmail dot com> 2012-01-11 22:54:34 UTC ---
(In reply to comment #8)
> It looks like target issue after all. I'm preparing a patch with following

OTOH, if the pattern says that it outputs to DImode pair (i.e. %eax/%edx, then
the whole pair is clobbered, no matter if any separate register is later used
or not. Due to this rationale, %edx should not be allocated and the patch from
comment #8 only papers over real problem.

To illustrate this problem further, following test clobbers %eax:

--cut here--
unsigned int  __attribute__((noinline))
test (int shift_size)
{
  unsigned long long res = ~0;

  res <<= shift_size;

  return res >> 32;
}
--cut here--

(insn 7 22 20 2 (parallel [
            (set (reg:DI 0 ax [65])
                (ashift:DI (const_int -1 [0xffffffffffffffff])
                    (reg:QI 2 cx [orig:63 shift_size ] [63])))
            (clobber (reg:CC 17 flags))
        ]) t.c:8 489 {*ashldi3_doubleword}
     (expr_list:REG_DEAD (reg:QI 2 cx [orig:63 shift_size ] [63])
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (expr_list:REG_UNUSED (reg:SI 0 ax)
                (expr_list:REG_EQUAL (ashift:DI (const_int -1
[0xffffffffffffffff])
                        (subreg:QI (reg/v:SI 2 cx [orig:63 shift_size ] [63])
0))
                    (nil))))))

peephole2 pass allocates SImode ax register as scratch:

(insn 31 30 32 2 (parallel [
            (set (reg:SI 0 ax)
                (const_int 0 [0]))
            (clobber (reg:CC 17 flags))
        ]) t.c:8 -1
     (nil))

(insn 32 31 33 2 (set (reg:CCZ 17 flags)
        (compare:CCZ (and:QI (reg:QI 2 cx [orig:63 shift_size ] [63])
                (const_int 32 [0x20]))
            (const_int 0 [0]))) t.c:8 -1
     (nil))

(insn 33 32 34 2 (set (reg:SI 1 dx [+4 ])
        (if_then_else:SI (ne (reg:CCZ 17 flags)
                (const_int 0 [0]))
            (reg:SI 0 ax [65])
            (reg:SI 1 dx [+4 ]))) t.c:8 -1
     (nil))

(insn 34 33 20 2 (set (reg:SI 0 ax [65])
        (if_then_else:SI (ne (reg:CCZ 17 flags)
                (const_int 0 [0]))
            (reg:SI 0 ax)
            (reg:SI 0 ax [65]))) t.c:8 -1
     (nil))

I'll speculate that (expr_list:REG_UNUSED (reg:SI 0 ax)) plays critical role
here.  Please compare this with (expr_list:REG_UNUSED (reg:SI 1 dx)) in the
pre-peephole2 pattern in Comment #4.