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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/52082] Memory loads not rematerialized
Date: Sun, 05 Sep 2021 04:52:28 +0000	[thread overview]
Message-ID: <bug-52082-4-6ieDKkRX30@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-52082-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=52082

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Severity|normal                      |enhancement

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
One thing I noticed that LLVM does to reduce the register pressure is:
(z ? v4 [k] : v3 [k])

Gets pulled out of the loop such that it is:
tmpaddr = z ? v4 : v3;

and then inside the loop it does:
(tempaddr)[k]

GCC still has (I changed the bb order just so it is easier to see what is going
on):
  if (z_39(D) != 0)
    goto <bb 9>; [50.00%]
  else
    goto <bb 11>; [50.00%]

  <bb 11> [local count: 5427362]:
  _21 = v3.3_18 + _157;
  iftmp.1_40 = *_21;
  goto <bb 10>; [100.00%]

  <bb 9> [local count: 5427362]:
  _17 = v4.2_14 + _157;
  iftmp.1_41 = *_17;

  <bb 10> [local count: 10854724]:
  # m_8 = PHI <iftmp.1_40(11), iftmp.1_41(9)>
  if (m_8 != 0B)
    goto <bb 12>; [94.50%]
  else
    goto <bb 19>; [5.50%]

we should able to do the similar it seems and need two less registers; one to
hold z and one to hold either v3 or v4.  This won't be enough for this testcase
but it will be something.

      parent reply	other threads:[~2021-09-05  4:52 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-02-01 10:30 [Bug middle-end/52082] New: " jakub at gcc dot gnu.org
2012-02-03  2:30 ` [Bug rtl-optimization/52082] " pinskia at gcc dot gnu.org
2021-09-05  4:52 ` pinskia at gcc dot gnu.org [this message]

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