[Bug middle-end/52306] [4.8/4.9 regression] ICE in cselib_record_set, at cselib.c:2158

["law at redhat dot com" <gcc-bugzilla@gcc.gnu.org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52306

Jeffrey A. Law <law at redhat dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |law at redhat dot com
           Assignee|unassigned at gcc dot gnu.org      |law at redhat dot com

--- Comment #28 from Jeffrey A. Law <law at redhat dot com> ---
The problem here is clearly reload.

reload has an optimization for reloading an input value of the current insn
where it looks at the prior insn to see if it sets the same (unallocated)
pseudo register.  If so and replacing the unallocated pseudo in the prior insn
results in an insn that is recognized and satisfies its constraints, then the
optimization is applied.

Perhaps RTL will make this clearly.  This is the key block after emitting
reload insns for insn 71:

(code_label 87 225 69 10 13 "" [1 uses])
(note 69 87 245 10 [bb 10] NOTE_INSN_BASIC_BLOCK)
(insn 245 69 70 10 (set (reg:SI 8 %a0)
        (reg/v/f:SI 7 %d7 [orig:43 cur ] [43])) j.c:44 -1
     (nil))
(insn 70 245 246 10 (set (reg/f:SI 0 %d0 [orig:46 D.1493 ] [46])
        (mem/f:SI (reg:SI 8 %a0) [3 cur_22->prefix+0 S4 A16])) j.c:44 39
{*movsi_m68k2}
     (nil))
(insn 246 70 247 10 (set (reg:SI 8 %a0)
        (reg:SI 54 [ ivtmp.11 ])) j.c:44 -1
     (nil))
(insn 247 246 71 10 (set (reg:SI 54 [ ivtmp.11 ])
        (plus:SI (reg:SI 54 [ ivtmp.11 ])
            (const_int 4 [0x4]))) j.c:44 141 {*addsi3_internal}
     (nil))
(insn 71 247 240 10 (set (reg/f:SI 48 [ D.1497 ])
        (mem/f:SI (post_inc:SI (reg:SI 8 %a0)) [3 MEM[base: 0B, index:
ivtmp.11_45, offset: 0B]+0 S4 A16])) j.c:44 39 {*movsi_m68k2}
     (expr_list:REG_INC (reg:SI 8 %a0)
        (expr_list:REG_INC (reg:SI 8 %a0)
            (nil))))
(note 240 71 73 NOTE_INSN_DELETED)
(insn 73 240 74 10 (set (cc0)
        (compare (reg/f:SI 0 %d0 [orig:46 D.1493 ] [46])
            (mem/f:SI (reg/f:SI 48 [ D.1497 ]) [3 _30->prefix+0 S4 A16])))
j.c:44 16 {*m68k.md:492}
     (expr_list:REG_DEAD (reg/f:SI 48 [ D.1497 ])
        (nil)))
(jump_insn 74 73 132 10 (set (pc)
        (if_then_else (eq (cc0)
                (const_int 0 [0]))
            (label_ref:SI 114)
            (pc))) j.c:44 405 {beq}
     (int_list:REG_BR_PROB 300 (nil))
 -> 114)



We are processing insn 73.  It has an input reload for (reg:SI 48).  The prior
insn (71) has (reg:SI 48) as its output.  So ideally whatever reload register
we use to satisfy (reg:SI 48) would be used for the output of 71 and the input
of 73.   In this specific case, the reload register selected for the input
reload of insn 73 is a0.  Substituting a0 for (reg:SI 48) results in insn 71
being a recognizable, successfully constrained insn, but it is ill-formed as it
uses a0 within an auto-increment addressing mode and elsewhere in the same
insn.

It's worth noting that the selection of a0 as the reload register for the input
value of insn 73 is legitimate.  It's only the back-substitution of a0 into the
output of insn 71 that is invalid.

A patch to address this properly in reload is in testing.