From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28375 invoked by alias); 12 Jun 2012 07:40:46 -0000 Received: (qmail 28189 invoked by uid 22791); 12 Jun 2012 07:40:44 -0000 X-SWARE-Spam-Status: No, hits=-4.3 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00,KHOP_THREADED X-Spam-Check-By: sourceware.org Received: from localhost (HELO gcc.gnu.org) (127.0.0.1) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 12 Jun 2012 07:40:29 +0000 From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/53639] x86_64: redundant 64-bit operations on 32-bit integers Date: Tue, 12 Jun 2012 07:40:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2012-06/txt/msg00656.txt.bz2 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53639 --- Comment #1 from Jakub Jelinek 2012-06-12 07:40:26 UTC --- Created attachment 27606 --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=27606 gcc48-pr53639.patch The first problem is that combiner combines: (insn 9 8 10 2 (parallel [ (set (reg:SI 74 [ D.1765 ]) (and:SI (reg/v:SI 60 [ vpn ]) (const_int 1023 [0x3ff]))) (clobber (reg:CC 17 flags)) ]) pr53639.c:19 378 {*andsi_1} (expr_list:REG_UNUSED (reg:CC 17 flags) (nil))) (insn 10 9 11 2 (set (reg:DI 75 [ D.1765 ]) (zero_extend:DI (reg:SI 74 [ D.1765 ]))) pr53639.c:19 112 {*zero_extendsidi2_rex64} (expr_list:REG_DEAD (reg:SI 74 [ D.1765 ]) (nil))) into: (insn 10 9 11 2 (parallel [ (set (reg:DI 75 [ D.1765 ]) (and:DI (subreg:DI (reg/v:SI 60 [ vpn ]) 0) (const_int 1023 [0x3ff]))) (clobber (reg:CC 17 flags)) ]) pr53639.c:19 377 {*anddi_1} (expr_list:REG_UNUSED (reg:CC 17 flags) (nil))) (expand_compound_operation in particular). But the presence of the DImode paradoxical subreg leads the RA to do the move in 64-bit rather than 32-bit. The attached untested patch cures that by splitting *anddi_1 into *andsi_1_zext so that the zero extension from SImode to DImode is done only on the result of the and. The second problem looks like RA decision, initially the SI 59 register (read from *q) and DI 80 register (zero_extend:DI (reg:SI 59)) are given the eax/rax register: Popping a2(r80,l0) -- assign reg 0 ... Popping a5(r59,l0) -- assign reg 0 but there is also an esi = (reg:SI 59) assignment in another code branch (set up of parameters for the tail call), so in the end IRA decides to put SI 59 into %esi register, but doesn't reconsider that the corresponding DI 80 register could be very well moved to that register as well: Assigning 4 to a5r59 Disposition: 5:r59 l0 4 6:r60 l0 1 4:r62 l0 2 0:r70 l0 0 3:r72 l0 5 8:r73 l0 4 7:r75 l0 2 1:r78 l0 1 2:r80 l0 0 Nothing afterwards fixes this up then. The REE pass does nothing, as the zero_extend uses different registers (%rax = zext (%esi)), so it doesn't eliminate the extension, and supposedly because of that other passes don't consider it worthwhile to rename the regs.